On 4 April 2011 18:19, Øyvind Harboe wrote:
>> Well, maybe I've missed something here. I've never had the need to debug the
>> 2nd core (often it is enabled by the OS, so bootloaders don't use it).
>> Anyway I wonder which is the suggested way to debug 2 cores at the same
>> time. Maybe start 2 op
On 4 April 2011 17:43, Øyvind Harboe wrote:
> Thanks for testing! That's a pretty good list to kick things off!
>
>> Features still to be implemented on PandaBoard (and all others Cortex-A*)
>> are:
>> - software breakpoints
>
> Presumably the issue here is how to deal with caching?
Yes... please
On 22 March 2011 01:53, luca ellero wrote:
> Unfortunately at the moment I have no cortex A8 boards to test it.
> Anyway I wonder where 0x8000 come from, since I can't find any docs in
This came from poking the omap4430. The ROM (on the two rev's I
tested, anyway) is bogus, so I don't think
On 21 March 2011 23:45, Øyvind Harboe wrote:
> Can anyone think of a good reason why we're
> duplicating these source files at this point?
These were duplicated because I didn't want to break anyone's A8 while
getting A9 support up. I think most (all?) of the A9 changes should be
correct for A8
On 10 March 2011 16:19, Peter Stuge wrote:
> Aaron Carroll wrote:
>> Soft breakpoints are currently broken if the MMU is enabled due to incorrect
>> cache flushing. Until this is fixed, force the use of hardware breakpoints.
>>
>> Signed-off-by: Aaron Carroll
>
&g
Signed-off-by: Aaron Carroll
---
tcl/board/ti_blaze.cfg |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
create mode 100644 tcl/board/ti_blaze.cfg
diff --git a/tcl/board/ti_blaze.cfg b/tcl/board/ti_blaze.cfg
new file mode 100644
index 000..c9bbe25
--- /dev/null
+++ b/tcl
Soft breakpoints are currently broken if the MMU is enabled due to incorrect
cache flushing. Until this is fixed, force the use of hardware breakpoints.
Signed-off-by: Aaron Carroll
---
tcl/target/omap4430.cfg |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/tcl
Hi Luca,
On 11 February 2011 02:00, du...@dummy.com wrote:
> On 10/02/2011 11.10, Aaron Carroll wrote:
>> On 10 February 2011 06:19, Luca Ellero wrote:
>>>
>>> This patch adds read/write capability to memory addresses not
>>> accessible through AHB-AP (for
Hi Luca,
On 10 February 2011 06:19, Luca Ellero wrote:
> This patch adds read/write capability to memory addresses not
> accessible through AHB-AP (for example "boot ROM code").
>
> To select between AHB and APB, a "dap apsel" command must be issued:
> dap apsel 0 -> following memory accesses are
Hi all,
I think the consensus on this issue is that AP handling could be
improved. Until someone has the motivation to fix it properly, can
this patch be applied? A9 reset is broken without it.
Thanks,
-- Aaron
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Openocd-development mailing list
Op
On 8 February 2011 09:47, Luca Ellero wrote:
> PandaBoard REV EA1 (Panda Early Adopter Program) has a different ID.
> This patch add alternate REV EA1 TAP id to configuration file
Confirming that the ID matches that of our PEAP Pandaboard.
-- Aaron
On 4 February 2011 17:00, Øyvind Harboe wrote:
> Maybe DAPs should exist independently of JTAG and
> targets and targets should refer to the DAP relevant
> to that target?
Also a good idea to be transport independent (SWD comes to mind).
But I don't understand oocd internals enough to see a nice
On 04/02/11 17:00, Øyvind Harboe wrote:
Maybe DAPs should exist independently of JTAG and
targets and targets should refer to the DAP relevant
to that target?
Agreed, but then how does one discover the DAP relevant to a TAP.
Suppose core0 is online and you're bringing up core1... all you have i
On 04/02/11 17:31, Mathias K. wrote:
Hello,
On 04.02.2011 01:38, Aaron Carroll wrote:
At a high level, I think it makes sense for functions to be explicit
about selecting an AP... I don't see any advantage to a "default".
I don't know if the AP always equal in a complet
Hi,
I'm about to start hacking on support for multiple targets per TAP.
Specifically this is for Cortex-A9, where a single TAP (ADIv5 DAP)
exposes several cores. The problem is that each core is a separate
target, but they need to share DAP data (struct adiv5_dap).
Currently, "struct adiv5_dap" i
On 03/02/11 17:33, Mathias K. wrote:
Hello,
i think it's better to fix ahbap_debugport_init. I have the same wrong
default AP on cortex_r4.
/* Default MEM-AP setup.
*
* REVISIT AP #0 may be an inappropriate default for this.
* Should we probe, or take a hint from the caller?
* Presumably we ca
Save, select and restore AP in cortex_a9_step and cortex_a9_init_debug_access.
Fixes a bug where the wrong AP is selected after a reset.
Signed-off-by: Aaron Carroll
---
src/target/cortex_a9.c | 26 --
1 files changed, 20 insertions(+), 6 deletions(-)
diff --git a/src
If a handler for the reset-assert event it present, skip the usual reset
handling. This is needed, for example, for board-level resets.
Signed-off-by: Aaron Carroll
---
src/target/cortex_m3.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/target
Fixes the reset bits of omap4430.cfg. To do this properly we need to be able to
override the M3's reset sequence, as can be done already on A8/A9, ARM11, etc.
Aaron Carroll (2):
cortex_m3: allow scripts to override reset
omap4430: fix reset sequence
src/target/cortex_m3.c |
* Write to the PRM reset control register should have been 'phys';
* Setup empty reset-assert handlers for the M3's, since the board-level reset
takes care of them;
* Remove the dbginit cruft, because it gets called implicitly on reset.
Signed-off-by: Aaron Carroll
---
tcl/targ
Hi Luca,
On 28/01/11 22:18, luca ellero wrote:
I think it would be easy to add a flag or similar to the memory dump
commands in OpenOCD to have the A9 issue memory accesses on behalf of
the debugger, so we can access resources on the L2 interconnect... it
is already like this on some CPUs. Not s
Signed-off-by: Aaron Carroll
---
doc/openocd.texi |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8ee328b..7772d78 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2633,7 +2633,7 @@ with this signal behave exactly like
Hi Luca,
On 28 January 2011 01:04, luca ellero wrote:
> I think it could be useful reporting here an opeonocd session with Mistral
> EVM3530 (OMAP 3530), _without_ an SD, so we are in an similar environment
> (3530 has boot ROM mapped at 0x14000, see OMAP 3530 TRM 25.4.2.1).
>
> Open On-Chip Debu
On 27 January 2011 16:53, Aaron Carroll wrote:
> I think I've got an x-loader fix for this... I'm trying to test it now
> with Linux. Stay tuned.
I think we have a winner... try this patch:
diff --git a/board/omap4430panda/clock.c b/board/omap4430panda/clock.c
index 792e5d6
Hi Luca,
On 26 January 2011 00:13, luca ellero wrote:
> With your patch it seems to work. Anyway after issuing "halt" instruction, I
> always get the following message:
>
> target state: halted
> target halted in Thumb state due to debug-request, current mode: Supervisor
> cpsr: 0x6173 pc: 0x
Hi Andreas,
This fixed the bug I was having with Cortex-A9 reset also. Thanks!
-- Aaron
On 26 January 2011 23:02, Spencer Oliver wrote:
> On 25/01/2011 02:03, Andreas Fritiofson wrote:
>>
>> ahbap_debugport_init was queueing reads to a local stack variable but
>> didn't execute the que
On 24 January 2011 19:29, Peter Stuge wrote:
> Aaron Carroll wrote:
>> +# GDB target: Cortex-A9, using DAP
>> +#
>> +# The debugger can connect to either core of the A9, but currently
>> +# not both simultaneously. Change -coreid to 1 to connect to the
>&
Signed-off-by: Aaron Carroll
---
tcl/board/ti_pandaboard.cfg |6 +++
tcl/target/omap4430.cfg | 106 +++
2 files changed, 112 insertions(+), 0 deletions(-)
create mode 100644 tcl/board/ti_pandaboard.cfg
create mode 100644 tcl/target/omap4430.cfg
Signed-off-by: Aaron Carroll
---
src/target/Makefile.am |4 +++-
src/target/target.c|2 ++
2 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 537c8c3..b6e8d4b 100644
--- a/src/target/Makefile.am
+++ b/src/target
ned-off-by: Aaron Carroll
---
src/target/target.c | 22 ++
src/target/target.h |1 +
2 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/src/target/target.c b/src/target/target.c
index 820e747..31ade6a 100644
--- a/src/target/target.c
+++ b/src/target/target.c
Signed-off-by: Aaron Carroll
---
.gitignore |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore
index 0491508..2812304 100644
--- a/.gitignore
+++ b/.gitignore
@@ -76,3 +76,6 @@ patches
# Emacs temp files
*~
+
+# CScope database files
Signed-off-by: Aaron Carroll
---
src/target/arm_dpm.h | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index e180807..b20184c 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -143,14 +143,20 @@ void
ks
get disabled. If anyone knows how to re-enable them, please get in
touch.
Cheers,
-- Aaron
Aaron Carroll (6):
Add cscope to .gitignore
Add '-coreid' target option to support multiple cores per TAP.
arm_dpm: add some SCR/RCR macros
cortex_a9: add source files for Corte
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