Hi Luca, On 28 January 2011 01:04, luca ellero <lro...@gmail.com> wrote: > I think it could be useful reporting here an opeonocd session with Mistral > EVM3530 (OMAP 3530), _without_ an SD, so we are in an similar environment > (3530 has boot ROM mapped at 0x14000, see OMAP 3530 TRM 25.4.2.1). > > Open On-Chip Debugger >> reset halt > RCLK not supported - fallback to 500 kHz > JTAG tap: omap3530.jrc tap/device found: 0x0b7ae02f (mfg: 0x017, part: > 0xb7ae, ver: 0x0) > JTAG tap: omap3530.dap enabled > omap3530.cpu: ran after reset and before halt ... > target state: halted > target halted in Thumb state due to debug-request, current mode: Supervisor > cpsr: 0x80000173 pc: 0x0001687c > MMU: disabled, D-Cache: disabled, I-Cache: enabled >> mdw 0x14000 > 0x00014000: a001a000 >> mdw 0x14000 10 > 0x00014000: a001a000 a003a002 a005a004 a007a006 a009a008 a00ba00a a00da00c > a00fa00e > 0x00014020: a011a010 a013a012 >> mdw 0x40014000 10 > 0x40014000: ea00022e e59ff018 e59ff018 e59ff018 e59ff018 e59ff018 e59ff018 > e59ff018 > 0x40014020: 288f48f7 4020ffc8 >> arm disassemble 0x40014000 > 0x40014000 0xea00022e B 0x400148c0 >> > > As you can see "mdw 0x14000" reports the weird pattern similar to yours on > 4430, but "mdw 0x40014000" report something which, I think, can be the real > ROM code. What do you think?
I've worked this out. You are right about the ROM addresses, both 0x28000 and 0x4002800 map to ROM. I don't understand why there is a duplicate mapping, but the initialization code uses 0x28000. The reason that you can't read the ROM through the debugger is because it reads memory through the AHB-AP, which sits on the L3 interconnect. However, the ROM is actually on the A9's internal L2 interconnect. On the L3, 0x40028000 doesn't map to anything. The 4430 TRM is a bit ambiguous, because it includes the ROM space in the "L3 Memory Space Mapping" table. I think it would be easy to add a flag or similar to the memory dump commands in OpenOCD to have the A9 issue memory accesses on behalf of the debugger, so we can access resources on the L2 interconnect... it is already like this on some CPUs. Not sure how useful it would be, though. Cheers, -- Aaron _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
