On Mon, May 02, 2011 at 03:24:00AM +0200, Øyvind Harboe wrote:
> Also, don't you need to flush the data cache somehow before
> invalidating the data cache?
Good question. I thought the arm926ejs write code, which feroceon
uses, was already doing that. But I really don't know enough about
this ar
Hi,
I have an issue regarding the WFI instruction on a STM32.
On the STM32, a particular bit must be set in order to maintain debug access
during sleep (WFI).
Imagine for a second a useless program where the first instruction is a WFI.
Currently I'm finding that OpenOCD cannot handle such a pr
Merged.
Thanks!
--
Øyvind Harboe
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Openocd-dev
Hi Eric,
thanks for the patch!
Some comments.
How to handle caches is sufficiently different that I don't
think we should try to make a generic model on how to
handle them. Check out some of the arm9's that do not have
data flushing implemented and how that's handled: write to
memory to populate
Feroceon has a layer 2 cache that must be invalidated after modifying
an instruction in memory to set or unset a breakpoint. Otherwise, the
CPU may continue to execute the original instruction out of the cache.
Added an "invalidate_l2" method to the arm7_9_common structure, in
case other sub-arch
On Thu, Apr 28, 2011 at 08:49:27PM -0400, Eric Cooper wrote:
> The Feroceon chip also has an L2 cache. I added some code to
> invalidate this when setting breakpoints, and now the target at
> least halts at the right place. But openocd doesn't notice it (I
> had to use poll to find out that it's
