On Thu, Apr 28, 2011 at 08:49:27PM -0400, Eric Cooper wrote: > The Feroceon chip also has an L2 cache. I added some code to > invalidate this when setting breakpoints, and now the target at > least halts at the right place. But openocd doesn't notice it (I > had to use poll to find out that it's halted) [...]
This second problem, as well as my original problem of ^C not working in gdb, seems to be due to my misconfiguration of the reset signals. Once I specified "srst_nogate" in the reset_config command, it started working correctly. (This is all black magic to me.) There are still some problems with single-stepping and continuing past breakpoints, but I'm getting there. -- Eric Cooper e c c @ c m u . e d u _______________________________________________ Openocd-development mailing list Openocd-development@lists.berlios.de https://lists.berlios.de/mailman/listinfo/openocd-development
