David Laight writes:
> From: Florian Fainelli
>> Sent: 27 November 2016 23:03
>> Le 27/11/2016 14:24, Timur Tabi a crit :
>> >> + * PHY device drivers in PHYLIB being reusable by nature, being able to
>> >> + configure correctly a specified delay enables more designs with
>> >> similar delay
>
From: Florian Fainelli
> Sent: 27 November 2016 23:03
> Le 27/11/2016 14:24, Timur Tabi a crit :
> >> + * PHY device drivers in PHYLIB being reusable by nature, being able to
> >> + configure correctly a specified delay enables more designs with
> >> similar delay
> >> + requirements to be ope
On 11/28/2016 11:15 AM, Mason wrote:
> On 28/11/2016 18:43, Florian Fainelli wrote:
>
>> On 11/28/2016 02:34 AM, Sebastian Frias wrote:
>>
>>> For what is worth, the Atheros at803x driver comes with RX delay enabled
>>> as per HW reset.
>>
>> Always, or is this a behavior possibly defined via a st
On 28/11/2016 18:43, Florian Fainelli wrote:
> On 11/28/2016 02:34 AM, Sebastian Frias wrote:
>
>> For what is worth, the Atheros at803x driver comes with RX delay enabled
>> as per HW reset.
>
> Always, or is this a behavior possibly defined via a stra-pin that can
> be changed?
Here's the data
On 11/28/2016 02:34 AM, Sebastian Frias wrote:
> On 27/11/16 19:44, Florian Fainelli wrote:
>> RGMII is a recurring source of pain for people with Gigabit Ethernet
>> hardware since it may require PHY driver and MAC driver level
>> configuration hints. Document what are the expectations from PHYLIB
On 27/11/16 19:44, Florian Fainelli wrote:
> RGMII is a recurring source of pain for people with Gigabit Ethernet
> hardware since it may require PHY driver and MAC driver level
> configuration hints. Document what are the expectations from PHYLIB and
> what options exist.
>
> Signed-off-by: Flori
Le 27/11/2016 à 14:24, Timur Tabi a écrit :
>> + * PHY device drivers in PHYLIB being reusable by nature, being able to
>> + configure correctly a specified delay enables more designs with
>> similar delay
>> + requirements to be operate correctly
>
> Ok, this one I don't know how to fix. I'm
Just some grammatical corrections. You might want to run a spellchecker
on all the patches.
Florian Fainelli wrote:
+ The Reduced Gigabit Medium Independent Interface (RGMII) is a 12 pins
"is a 12-pin"
+ electrical signal interface using a synchronous 125Mhz clock signal and
several
+ dat
RGMII is a recurring source of pain for people with Gigabit Ethernet
hardware since it may require PHY driver and MAC driver level
configuration hints. Document what are the expectations from PHYLIB and
what options exist.
Signed-off-by: Florian Fainelli
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Documentation/networking/phy.txt | 76
