From: Vivien Didelot
Date: Fri, 4 Nov 2016 03:23:25 +0100
> The Marvell chips have one internal SMI device per port, containing a
> set of registers used to configure a port's link, STP state, default
> VLAN or addresses database, etc.
>
> This patchset creates port files to implement the port
On Fri, Nov 04, 2016 at 03:23:25AM +0100, Vivien Didelot wrote:
> The Marvell chips have one internal SMI device per port, containing a
> set of registers used to configure a port's link, STP state, default
> VLAN or addresses database, etc.
Reviewed-by: Andrew Lunn
Andrew
The Marvell chips have one internal SMI device per port, containing a
set of registers used to configure a port's link, STP state, default
VLAN or addresses database, etc.
This patchset creates port files to implement the port operations as
described in datasheets, and extend the chip ops structur
