David S. Miller wrote:
> Applied, but that IBM stuff seems bogus. Even a PCI config space
> access that is implemented via a Hypervisor call should not take that
> long.
>
In the memory test, we are reading and writing different patterns to
the entire SRAM, so it's not too surprising to me that
From: "Michael Chan" <[EMAIL PROTECTED]>
Date: Mon, 27 Mar 2006 17:09:33 -0800
> Speed up SRAM read and write functions if possible by using MMIO
> instead of config. cycles. With this change, the post reset signature
> done at the end of D3 power change must now be moved before the D3
> power cha
Speed up SRAM read and write functions if possible by using MMIO
instead of config. cycles. With this change, the post reset signature
done at the end of D3 power change must now be moved before the D3
power change.
IBM reported a problem on powerpc blades during ethtool self test
that was caused
