Hi Jakub,
On Tue, Mar 16, 2021 at 10:53 PM Jakub Kicinski wrote:
>
> On Tue, 16 Mar 2021 14:57:08 +0530 Hariprasad Kelam wrote:
> > From: Subbaraya Sundeep
> >
> > TOS overlaps with DMAC field in mcam search key and hence installing
> > rules for TX side are failing. Hence remove TOS field from
On Wed, Mar 17, 2021 at 1:57 AM Jakub Kicinski wrote:
>
> On Tue, 16 Mar 2021 23:33:40 +0530 sundeep subbaraya wrote:
> > On Tue, Mar 16, 2021 at 10:53 PM Jakub Kicinski wrote:
> > >
> > > On Tue, 16 Mar 2021 14:57:07 +0530 Hariprasad Kelam wrote:
&
Hi Jakub,
On Tue, Mar 16, 2021 at 10:53 PM Jakub Kicinski wrote:
>
> On Tue, 16 Mar 2021 14:57:07 +0530 Hariprasad Kelam wrote:
> > From: Subbaraya Sundeep
> >
> > Memory for driver private structure rvu_devlink is
> > also allocated during devlink_alloc. Hence use
> > the allocated memory by d
Tested-by: Subbaraya Sundeep
On Mon, Feb 8, 2021 at 7:27 AM Kevin Hao wrote:
>
> Pavel pointed that the return of dma_addr_t in
> otx2_alloc_rbuf/__otx2_alloc_rbuf() seem suspicious because a negative
> error code may be returned in some cases. For a dma_addr_t, the error
> code such as -ENOMEM
Tested-by: Subbaraya Sundeep
Thanks,
Sundeep
On Sun, Jan 31, 2021 at 1:49 PM Kevin Hao wrote:
>
> The napi_alloc_frag_align() will guarantee that a correctly align
> buffer address is returned. So use this function to simplify the buffer
> alloc and avoid the unnecessary memory waste.
>
> Signe
Hi Kevin,
Tested at my end and works fine. Thanks for the patch.
Tested-by: Subbaraya Sundeep
Sundeep
On Thu, Jan 21, 2021 at 12:51 PM Kevin Hao wrote:
>
> The octeontx2 hardware needs the buffer to be 128 byte aligned.
> But in the current implementation of napi_alloc_frag(), it can't
> guar
Thanks Jakub,
Sundeep
On Sun, Nov 1, 2020 at 3:35 AM Jakub Kicinski wrote:
>
> On Thu, 29 Oct 2020 10:45:39 +0530 sundeep.l...@gmail.com wrote:
> > From: Subbaraya Sundeep
> >
> > OcteonTx2 series of silicons have multiple variants, the
> > 98xx variant has two network interface controllers (NI
Hi Jakub,
On Sun, Oct 18, 2020 at 9:41 PM Jakub Kicinski wrote:
>
> On Sat, 17 Oct 2020 10:22:26 +0530 sundeep subbaraya wrote:
> > > Let me rephrase the question - can the AF driver only run on the SoC
> > > or are there configurations in which host can control the AF
Hi Jakub,
On Fri, Oct 16, 2020 at 11:18 PM Jakub Kicinski wrote:
>
> On Fri, 16 Oct 2020 08:59:43 +0530 sundeep subbaraya wrote:
> > On Thu, Oct 15, 2020 at 9:02 PM Jakub Kicinski wrote:
> > > On Thu, 15 Oct 2020 17:53:07 +0530 sundeep subbaraya wrote:
> > > >
Hi Jesse Branderburg,
On Thu, Oct 15, 2020 at 9:27 PM Jesse Brandeburg
wrote:
>
> sundeep.l...@gmail.com wrote:
>
> > From: Subbaraya Sundeep
> >
> > Since multiple blocks of same type are present in
> > 98xx, modify functions which get resource count and
> > which update resource count to work
Hi Jakub,
On Thu, Oct 15, 2020 at 9:02 PM Jakub Kicinski wrote:
>
> On Thu, 15 Oct 2020 17:53:07 +0530 sundeep subbaraya wrote:
> > Hi Jakub,
> >
> > On Thu, Oct 15, 2020 at 8:18 AM Jakub Kicinski wrote:
> > >
> > > On Tue, 13 Oct 2020 1
Hi Jakub,
On Thu, Oct 15, 2020 at 8:18 AM Jakub Kicinski wrote:
>
> On Tue, 13 Oct 2020 15:56:28 +0530 sundeep.l...@gmail.com wrote:
> > -static const struct npc_mcam_kex npc_mkex_default = {
> > +static struct npc_mcam_kex npc_mkex_default = {
> > .mkex_sign = MKEX_SIGN,
> > .name =
Hi Jakub,
On Tue, Sep 22, 2020 at 4:48 AM Jakub Kicinski wrote:
>
> On Mon, 21 Sep 2020 22:32:41 +0530 sundeep.l...@gmail.com wrote:
> > diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.c
> > b/drivers/net/ethernet/marvell/octeontx2/af/rvu_trace.c
> > new file mode 100644
> > ind
On Thu, Sep 17, 2020 at 11:34 AM Jiri Pirko wrote:
>
> Wed, Sep 16, 2020 at 07:19:36PM CEST, sundeep.l...@gmail.com wrote:
> >On Wed, Sep 16, 2020 at 4:04 PM Jiri Pirko wrote:
> >>
> >> Mon, Sep 07, 2020 at 12:59:45PM CEST, sundeep.l...@gmail.com wrote:
> >> >Hi Jakub,
> >> >
> >> >On Sat, Sep 5,
On Wed, Sep 16, 2020 at 4:04 PM Jiri Pirko wrote:
>
> Mon, Sep 07, 2020 at 12:59:45PM CEST, sundeep.l...@gmail.com wrote:
> >Hi Jakub,
> >
> >On Sat, Sep 5, 2020 at 2:07 AM Jakub Kicinski wrote:
> >>
> >> On Fri, 4 Sep 2020 12:29:04 + Sunil Kovvuri Goutham wrote:
> >> > > >No, there are 3 dri
Hi Jiri,
On Mon, Sep 7, 2020 at 4:29 PM sundeep subbaraya wrote:
>
> Hi Jakub,
>
> On Sat, Sep 5, 2020 at 2:07 AM Jakub Kicinski wrote:
> >
> > On Fri, 4 Sep 2020 12:29:04 + Sunil Kovvuri Goutham wrote:
> > > > >No, there are 3 drivers regist
On Tue, Sep 15, 2020 at 9:42 PM Jakub Kicinski wrote:
>
> On Tue, 15 Sep 2020 21:22:21 +0530 sundeep subbaraya wrote:
> > > > Make use of the standard devlink tracepoint wherever applicable, and you
> > > > can keep your extra ones if you want (as long as Jiri don&#
Hi Jakub,
On Sat, Sep 5, 2020 at 2:07 AM Jakub Kicinski wrote:
>
> On Fri, 4 Sep 2020 12:29:04 + Sunil Kovvuri Goutham wrote:
> > > >No, there are 3 drivers registering to 3 PCI device IDs and there can
> > > >be many instances of the same devices. So there can be 10's of instances
> > > >of
Hi David,
On Mon, Aug 24, 2020 at 6:47 PM David Miller wrote:
>
> From: David Miller
> Date: Mon, 24 Aug 2020 06:16:57 -0700 (PDT)
>
> > Series applied, thank you.
>
> Actually, this doesn't even compile:
>
Our Marvell GCC10 ARM64 compiler did not complain anything about this
even with W=1 and m
Hi,
On Wed, Aug 19, 2020 at 10:30 PM Jesse Brandeburg
wrote:
>
> sundeep.l...@gmail.com wrote:
>
> > From: Aleksey Makarov
> >
> > This patch adds PTP clock and uses it in Octeontx2
> > network device. PTP clock uses mailbox calls to
> > access the hardware counter on the RVU side.
> >
> > Co-de
Hi,
On Wed, Aug 19, 2020 at 9:30 PM Jesse Brandeburg
wrote:
>
> sundeep.l...@gmail.com wrote:
>
> > From: Aleksey Makarov
> >
> > This patch adds driver for Precision Time
> > Protocol Clock and Timestamping block found on
> > Octeontx2 platform. The driver does initial
> > configuration and exp
Hi,
On Wed, Aug 19, 2020 at 9:08 PM Jesse Brandeburg
wrote:
>
> sundeep.l...@gmail.com wrote:
>
> > From: Zyta Szpak
> >
> > Four new mbox messages ids and handler are added in order to
> > enable or disable timestamping procedure on tx and rx side.
> > Additionally when PTP is enabled, the pack
Hi Srujana,
On Fri, Jul 24, 2020 at 6:39 PM Srujana Challa wrote:
>
> The following series adds support for Marvell Cryptographic Acceleration
> Unit(CPT) on OcteonTX2 CN96XX SoC.
> This series is tested with CRYPTO_EXTRA_TESTS enabled and
> CRYPTO_DISABLE_TESTS disabled.
>
> Srujana Challa (4):
Hi David,
On Sat, Jul 25, 2020 at 8:40 AM David Miller wrote:
>
> From: sundeep subbaraya
> Date: Fri, 24 Jul 2020 08:40:44 +0530
>
> > On Fri, Jul 24, 2020 at 12:43 AM David Miller wrote:
> >>
> >> If you leave interrupts on then an interrupt can arrive af
Hi David,
On Fri, Jul 24, 2020 at 12:43 AM David Miller wrote:
>
> From: sundeep subbaraya
> Date: Thu, 23 Jul 2020 20:29:03 +0530
>
> > Hi David,
> >
> > On Wed, Jul 22, 2020 at 7:34 PM sundeep subbaraya
> > wrote:
> >>
> >> Hi David,
Hi David,
On Wed, Jul 22, 2020 at 7:34 PM sundeep subbaraya
wrote:
>
> Hi David,
>
> On Wed, Jul 22, 2020 at 4:47 AM David Miller wrote:
> >
> > From: sundeep.l...@gmail.com
> > Date: Tue, 21 Jul 2020 22:44:05 +0530
> >
> > > Subbaraya Sundeep (
Hi David,
On Wed, Jul 22, 2020 at 4:47 AM David Miller wrote:
>
> From: sundeep.l...@gmail.com
> Date: Tue, 21 Jul 2020 22:44:05 +0530
>
> > Subbaraya Sundeep (3):
> > octeontx2-pf: Fix reset_task bugs
> > octeontx2-pf: cancel reset_task work
> > octeontx2-pf: Unregister netdev at driver re
Hi David,
On Fri, Jul 17, 2020 at 11:33 PM David Miller wrote:
>
> From: Jakub Kicinski
> Date: Fri, 17 Jul 2020 10:48:12 -0700
>
> > On Fri, 17 Jul 2020 10:41:49 +0530 sundeep subbaraya wrote:
> >> I can separate this out and put in another patch #4 if you insist.
&
Hi Jakub,
On Fri, Jul 17, 2020 at 11:18 PM Jakub Kicinski wrote:
>
> On Fri, 17 Jul 2020 10:41:49 +0530 sundeep subbaraya wrote:
> > On Fri, Jul 17, 2020 at 5:41 AM Jakub Kicinski wrote:
> > > On Wed, 15 Jul 2020 18:08:09 +0530 Subbaraya Sundeep wrote:
> > > >
Hi Jakub,
On Fri, Jul 17, 2020 at 5:41 AM Jakub Kicinski wrote:
>
> On Wed, 15 Jul 2020 18:08:09 +0530 Subbaraya Sundeep wrote:
> > @@ -1730,10 +1745,149 @@ static void otx2_reset_task(struct work_struct
> > *work)
> > if (!netif_running(pf->netdev))
> > return;
> >
> > +
Hi Richard,
On Thu, Jul 9, 2020 at 9:32 PM Richard Cochran wrote:
>
> On Thu, Jul 09, 2020 at 06:57:01PM +0530, sundeep.l...@gmail.com wrote:
>
> > @@ -1736,6 +1751,143 @@ static void otx2_reset_task(struct work_struct
> > *work)
> > netif_trans_update(pf->netdev);
> > }
> >
> > +static i
Hi Jakub,
On Wed, Jul 8, 2020 at 11:10 PM Jakub Kicinski wrote:
>
> On Wed, 8 Jul 2020 22:20:18 +0530 sundeep.l...@gmail.com wrote:
> > From: Aleksey Makarov
> >
> > This patch adds PTP clock and uses it in Octeontx2
> > network device. PTP clock uses mailbox calls to
> > access the hardware co
Hi David,
Please let me know any other mailing list or persons I need to add.
Thanks,
Sundeep
On Fri, Jan 5, 2018 at 12:07 PM, sundeep subbaraya
wrote:
> Hi,
>
> I am quite new to IPv6.
> I ran to one problem hope you guys can help me.
> I have multiple ethernet port box which r
Hi,
I am quite new to IPv6.
I ran to one problem hope you guys can help me.
I have multiple ethernet port box which runs by Altera's Cyclone 5.
I am using source based policy routing for ipv6.
The problem is when there is "default via " entry in per interface
routing table then ping to a link loca
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