HI Andreas, Zong:
On Fri, Mar 19, 2021 at 4:51 PM Andreas Schwab wrote:
>
> On Mär 19 2021, Yixun Lan wrote:
>
> > what's the exact root cause? and any solution?
>
> Try reverting the five commits starting with
> 732374a0b440d9a79c8412f318a25cd37ba6f4e2.
>
I conf
HI Andreas:
On Fri, Mar 19, 2021 at 8:28 AM Yixun Lan wrote:
>
> HI Andreas:
>
> On Wed, Mar 17, 2021 at 4:27 PM Andreas Schwab wrote:
> >
> > It turned out to be a broken clock driver.
> >
>
> what's the exact root cause? and any solution?
> seems I
HI Andreas:
On Wed, Mar 17, 2021 at 4:27 PM Andreas Schwab wrote:
>
> It turned out to be a broken clock driver.
>
what's the exact root cause? and any solution?
seems I face the same issue, upgrade kernel to 5.11, then eth0 fail to bring up
Yixun Lan
Yixun Lan (2):
dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
net: stmmac: dwmac-meson: extend phy mode setting
.../devicetree/bindings/net/meson-dwmac.txt | 1 +
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++---
2 files changed, 105 insertions(+), 16
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan
---
Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
1 file
configuration need to be changed to
value - b100.
This patch was verified with a RTL8201F 100M ethernet PHY.
Signed-off-by: Yixun Lan
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 120 +++---
1 file changed, 104 insertions(+), 16 deletions(-)
diff --git a/drivers/net/ethernet
Hi Jerome
On 04/26/18 16:47, Jerome Brunet wrote:
> On Thu, 2018-04-26 at 16:05 +0000, Yixun Lan wrote:
>> In the Meson-AXG SoC, the phy mode setting of PRG_ETH0 in the glue layer
>> is extended from bit[0] to bit[2:0].
>> There is no problem if we configure it to the
configuration need to be changed to
value - b100.
This patch was verified with a RTL8201F 100M ethernet PHY.
Signed-off-by: Yixun Lan
---
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 95 ---
1 file changed, 84 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet
We need to introduce a new compatible name for the Meson-AXG SoC
in order to support the RMII 100M ethernet PHY, since the PRG_ETH0
register of the dwmac glue layer is changed from previous old SoC.
Signed-off-by: Yixun Lan
---
Documentation/devicetree/bindings/net/meson-dwmac.txt | 1 +
1 file
Due to the dwmac glue layer register changed, we need to
introduce a new compatible name for the Meson-AXG SoC
to support for the RMII 100M ethernet PHY.
Yixun Lan (2):
dt-bindings: net: meson-dwmac: new compatible name for AXG SoC
net: stmmac: dwmac-meson: extend phy mode setting
HI Jerome
On 01/17/18 01:19, Jerome Brunet wrote:
> On Tue, 2018-01-16 at 12:17 +0100, Martin Blumenstingl wrote:
Hi Martin
I'm having problem with this series applied.
I've tested on the A113D (AXG) platform, if this patch is applied, the
driver will choose MPLL2 as clk
On 01/16/18 01:10, Martin Blumenstingl wrote:
> Hi Dave,
>
> this series is now successfully tested, thus we think it's ready to be
> applied to your net-next tree.
>
> Emiliano reported [0] that he couldn't get dwmac-meson8b to work on his
> Odroid-C1. This is the (hopefully) final version of
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
Reviewed-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 +
ists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
[6] git://github.com/BayLibre/clk-meson.git
Yixun Lan (2):
ARM64: dt
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
HI Kevin
On 12/16/2017 03:29 AM, Kevin Hilman wrote:
> Yixun Lan writes:
>
>> Add DT info for the stmmac ethernet MAC which found in
>> the Amlogic's Meson-AXG SoC, also describe the ethernet
>> pinctrl & clock information here.
>>
>> Reviewed-by
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
Reviewed-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 54 +
ail/linux-amlogic/2017-December/005768.html
[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
Yixun Lan (2):
ARM64: dts
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
Hi Jerome:
On 12/15/17 00:45, Jerome Brunet wrote:
> On Thu, 2017-12-14 at 11:02 +0800, Yixun Lan wrote:
>> ---
>> Changes in v2 since [1]:
>> - rebase to kevin's v4.16/dt64 branch
>> - add Neil's Reviewed-by
>> - move clock info to board.dts inste
-by: Neil Armstrong
Signed-off-by: Yixun Lan
---
Changes in v2 since [1]:
- rebase to kevin's v4.16/dt64 branch
- add Neil's Reviewed-by
- move clock info to board.dts instead of in soc.dtsi
- drop "meson-axg-dwmac" compatible string, since we didn't use this
we could
HI Jerome:
On 12/05/17 17:33, Jerome Brunet wrote:
> From: Neil Armstrong
>
> Define registers and bits in meson-gxl PHY driver to make a bit
> more human friendly. No functional change
>
> Signed-off-by: Neil Armstrong
> Signed-off-by: Jerome Brunet
> ---
> drivers/net/phy/meson-gxl.c | 11
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Signe
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