This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.

Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
Signed-off-by: Yixun Lan <yixun....@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts 
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..8932654f5090 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -17,6 +17,13 @@
        };
 };
 
+&ethmac {
+       status = "okay";
+       phy-mode = "rgmii";
+       pinctrl-0 = <&eth_rgmii_y_pins>;
+       pinctrl-names = "default";
+};
+
 &uart_AO {
        status = "okay";
 };
-- 
2.15.1

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