On Thu, Jan 07, 2021 at 03:51:38PM +0100, Andrew Lunn wrote:
> On Thu, Jan 07, 2021 at 10:26:12AM +0100, Greg KH wrote:
> > On Thu, Jan 07, 2021 at 02:07:08PM +0800, Xu Yilun wrote:
> > > This driver supports the ethernet retimers (C827) for the Intel PAC
> > > (Pro
On Thu, Jan 07, 2021 at 10:26:12AM +0100, Greg KH wrote:
> On Thu, Jan 07, 2021 at 02:07:08PM +0800, Xu Yilun wrote:
> > This driver supports the ethernet retimers (C827) for the Intel PAC
> > (Programmable Acceleration Card) N3000, which is a FPGA based Smart NIC.
> >
&
10 BMC firmware. They are configured in 4 ports
10G/25G retimer mode. Host could query their link states and firmware
version information via retimer interfaces (Shared registers) on Intel
MAX 10 BMC. The driver creates sysfs interfaces for users to query these
information.
Signed-off-by: Xu Yilun
ib.
https://github.com/OPAE/opae-sdk/
Generally it facilitate the development on all the DFL (Device Feature
List) based FPGA Cards, including the management of static region &
dynamic region reprogramming, accelerators accessing and the board
specific peripherals.
Xu Yilun (2):
mfd: intel-m
could query them via
retimer interfaces (shared registers) on the BMC. The 2 retimers have
identical register interfaces in different register addresses or fields,
so it is better we define 2 retimer devices and handle them with the same
driver.
Signed-off-by: Xu Yilun
---
drivers/mfd/intel-m10-
Hi Andrew:
On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote:
> > > > > Do you really mean PHY? I actually expect it is PCS?
> > > >
> > > > For this implementation, yes.
> > >
> > > Yes, you have a PHY? Or Yes, it is PCS?
> >
> > Sorry, I mean I have a PHY.
> >
> > >
> > > To me,
On Mon, Oct 26, 2020 at 08:14:00PM +0100, Andrew Lunn wrote:
> > > > > Do you really mean PHY? I actually expect it is PCS?
> > > >
> > > > For this implementation, yes.
> > >
> > > Yes, you have a PHY? Or Yes, it is PCS?
> >
> > Sorry, I mean I have a PHY.
> >
> > >
> > > To me, the phylib m
On Mon, Oct 26, 2020 at 11:35:52AM -0700, Jakub Kicinski wrote:
> On Tue, 27 Oct 2020 01:38:04 +0800 Xu Yilun wrote:
> > > > The line/host side Ether Group is not the terminal of the network data
> > > > stream.
> > > > Eth1 will not paticipa
On Mon, Oct 26, 2020 at 02:00:01PM +0100, Andrew Lunn wrote:
> > > > +The Intel(R) PAC N3000 is a FPGA based SmartNIC platform for
> > > > multi-workload
> > > > +networking application acceleration. A simple diagram below to for the
> > > > board:
> > > > +
> > > > + +---
Hi Andrew
Thanks for your fast response, see comments inline.
On Fri, Oct 23, 2020 at 05:37:31PM +0200, Andrew Lunn wrote:
> Hi Xu
>
> Before i look at the other patches, i want to understand the
> architecture properly.
I have a doc to describe the architecture:
https://www.intel.com/content/
This patch makes preparation for supporting DFL Ether Group private
feature driver, which reads bitstream_id.vendor_net_cfg field to
determin the interconnection of network components on FPGA device.
Signed-off-by: Xu Yilun
---
drivers/fpga/dfl-fme-main.c | 10 ++
drivers/fpga/dfl.c
This patch adds an API for dfl devices to find which physical device
owns the DFL.
This patch makes preparation for supporting DFL Ether Group private
feature driver. It uses this information to determine which retimer
device physically connects to which ether group.
Signed-off-by: Xu Yilun
25G configurations. Support for 10G will be in
other patches.
Signed-off-by: Xu Yilun
Signed-off-by: Russ Weight
---
.../ABI/testing/sysfs-class-net-dfl-eth-group | 19 +
drivers/net/ethernet/intel/Kconfig | 18 +
drivers/net/ethernet/intel/Makefile| 2 +
drivers
ther Group driver for 25G.
Patch #6 adds 10G support for the Ether Group driver.
Xu Yilun (6):
docs: networking: add the document for DFL Ether Group driver
fpga: dfl: export network configuration info for DFL based FPGA
fpga: dfl: add an API to get the base device for dfl device
ethernet:
bus, it creates a virtual
mdio bus for each NIC device instance, and a dedicated phy driver which
only provides the supported features and link state.
A DFL Ether Group driver will create net devices and connect to these
phys.
Signed-off-by: Xu Yilun
---
drivers/fpga/dfl-n3000-nios.c
This patch adds 10G configurations support for dfl ether group private
feature.
10G configurations have different PHY & MAC IP blocks from 25G, so a
different set of HW operations is implemented, but the software arch is
quite similar with 25G.
Signed-off-by: Xu Yilun
Signed-off-by: Russ We
This patch adds the document for DFL Ether Group driver.
Signed-off-by: Xu Yilun
---
.../networking/device_drivers/ethernet/index.rst | 1 +
.../ethernet/intel/dfl-eth-group.rst | 102 +
2 files changed, 103 insertions(+)
create mode 100644
Documentation
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