On 7/8/20 2:23 AM, Ooi, Joyce wrote:
From: Dalon Westergreen
Add support for the ptp clock used with the tse, and update
the driver to support timestamping when enabled. We also
enable debugfs entries for the ptp clock to allow some user
control and interaction with the ptp clock.
Cc: Richard
_tse_private *priv,
+struct tse_buffer *buffer);
u32 (*tx_completions)(struct altera_tse_private *priv);
void (*add_rx_desc)(struct altera_tse_private *priv,
struct tse_buffer *buffer);
Reviewed-by: Thor Thayer
/* __ALTERA_SGDMA_H__ */
Reviewed-by: Thor Thayer
addr);
+}
+
+static inline
+void csrwr8(u8 val, void __iomem *mac, size_t offs)
+{
+ void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+ writeb(val, paddr);
+}
#endif /* __ALTERA_UTILS_H__*/
Reviewed-by: Thor Thayer
L,
};
static const struct of_device_id altera_tse_ids[] = {
Reviewed-by: Thor Thayer
(*get_rx_status)(struct altera_tse_private *priv);
+ int (*init_dma)(struct altera_tse_private *priv);
+ void (*uninit_dma)(struct altera_tse_private *priv);
+ void (*start_rxdma)(struct altera_tse_private *priv);
};
/* This structure is private to each device.
Reviewed-by: Thor
. */
- priv->rx_ring_size = dma_rx_num;
- priv->tx_ring_size = dma_tx_num;
ret = alloc_init_skbufs(priv);
if (ret) {
netdev_err(dev, "DMA descriptors initialization failed\n");
Reviewed-by: Thor Thayer
;dmaops->tx_buffer(priv, buffer);
+ if (ret)
+ goto out;
skb_tx_timestamp(skb);
Reviewed-by: Thor Thayer
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls as
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
Reviewed-by: Rob Herring
---
v2 New compatible string and usage for Stratix10
v3 No change
v4 Add Reviewed-by from v2.
---
.../devicetree/bindings/arm/altera/socfpga-system.txt
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c8432e24207e..48a312126cf7
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required, this
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2-4 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager compatible
v3 Use "altr,sys-mgr" as the non-specific compatib
Hi Joyce,
On 2/12/19 10:24 AM, Ooi, Joyce wrote:
As there is restriction to access to EMAC System Manager registers in
the kernel for Intel Stratix10, the use of SMC calls are required and
added in dwmac-socfpga driver.
Signed-off-by: Ooi, Joyce
I have a pending patchset[1] that addresses
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform. Use "altr,sys-mgr" as the non-specific
fallback compatible.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager com
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required, this
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2-3 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2-3 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c8432e24207e..48a312126cf7
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
---
v2 New compatible string and usage for Stratix10
v3 No change
---
.../devicetree/bindings/arm/altera/socfpga-system.txt| 12
1 file changed, 12 insertions
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls as
/* Check for buffered last packet */
status = csrrd32(priv->tx_dma_csr, msgdma_csroffs(status));
Thanks for the patch!
Acked-by: Thor Thayer
On 1/21/19 2:29 AM, Atsushi Nemoto wrote:
From: Tomonori Sakita
If fill_level was not zero and status was not BUSY,
result of "tx_prod - tx_cons - inuse" might be zero.
Subtracting 1 unconditionally results invalid negative return value
on this case.
The subtraction is not needed if fill_leve
ach to PHY\n");
+ phydev = NULL;
+ }
} else {
int ret;
Thanks for the patch!
Acked-by: Thor Thayer
From: Thor Thayer
Add MFD driver for SOCFPGA System Manager to handle
System Manager calls differently for ARM32 vs ARM64.
The SOCFPGA System Manager includes registers from several
SOC peripherals.
On ARM32, syscon handles this aggregated register grouping.
Implement System Manager calls as
From: Thor Thayer
The SOCFPGA System Manager register block aggregates different
peripheral functions into one area.
On 32 bit ARM parts, handle in the same way as syscon.
On 64 bit ARM parts, the System Manager can only be accessed by
EL3 secure mode. Since a SMC call to EL3 is required, this
From: Thor Thayer
Add the device tree bindings for the Stratix10 System Manager.
Signed-off-by: Thor Thayer
---
v2 New compatible string and usage for Stratix10
---
.../devicetree/bindings/arm/altera/socfpga-system.txt| 12
1 file changed, 12 insertions(+)
diff --git a
From: Thor Thayer
Add System Manager driver by default for SOCFPGA ARM32 platforms.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm/configs/socfpga_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/socfpga_defconfig
b/arch/arm/configs/socfpga_defconfig
From: Thor Thayer
The ARM64 System Manager requires a different method of reading
the System Manager than ARM32. A new System Manager driver was
created to steer ARM32 System Manager calls to regmap_mmio and
ARM64 System Manager calls to the new access method.
Convert from syscon to the shared
From: Thor Thayer
Use the new compatible string defined for the Stratix10
System Manager. Remove syscon since it is not correct
on this platform.
Signed-off-by: Thor Thayer
---
v2 New. Use new Stratix10 System Manager compatible
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
1
From: Thor Thayer
Enable the Stratix10 System Manager by default.
Signed-off-by: Thor Thayer
---
v2 No change
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9a57d11330b..873d807bb82b
gned int txsize = priv->tx_ring_size;
Acked-by: Thor Thayer
r identifier names.
> ---
> drivers/net/ethernet/altera/altera_msgdma.h | 30 ++-
> drivers/net/ethernet/altera/altera_sgdma.h | 32 +++------
Acked-by: Thor Thayer
rwr8(u8 val, void __iomem *mac, size_t offs)
+{
+ void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+ writeb(val, paddr);
+}
#endif /* __ALTERA_UTILS_H__*/
Acked-by: Thor Thayer
a = {
@@ -1677,6 +1681,7 @@ static const struct altera_dmaops altera_dtype_msgdma = {
.init_dma = msgdma_initialize,
.uninit_dma = msgdma_uninitialize,
.start_rxdma = msgdma_start_rxdma,
+ .start_txdma = NULL,
};
static const struct of_device_id altera_tse_id
)(struct altera_tse_private *priv);
+ void (*uninit_dma)(struct altera_tse_private *priv);
+ void (*start_rxdma)(struct altera_tse_private *priv);
};
/* This structure is private to each device.
Acked-by: Thor Thayer
x_ring_size = dma_tx_num;
ret = alloc_init_skbufs(priv);
if (ret) {
netdev_err(dev, "DMA descriptors initialization failed\n");
Acked-by: Thor Thayer
t;tx_buffer(priv, buffer);
+ if (ret)
+ goto out;
skb_tx_timestamp(skb);
If the content hasn't changed, you can just include my previous Acked-by
under your Signed-off-by in the subsequent versions. For now though,
Acked-by: Thor Thayer
Hi Arnd,
On 12/14/18 6:36 AM, Arnd Bergmann wrote:
On Tue, Nov 13, 2018 at 5:03 PM wrote:
From: Thor Thayer
The SOCFPGA System Manager register block aggregate different
peripheral functions into one place.
On 32 bit ARM parts, the syscon framework fits this problem well.
On 64 bit ARM
Hi Dalon,
Just a few comments/questions.
On 11/14/18 6:50 PM, Dalon Westergreen wrote:
From: Dalon Westergreen
Add support for the mSGDMA prefetcher. The prefetcher adds support
for a linked list of descriptors in system memory. The prefetcher
feeds these to the mSGDMA dispatcher.
The pref
+ Rob Herring, Mark Rutland and the Device Tree mailing list.
On 11/14/18 6:50 PM, Dalon Westergreen wrote:
From: Dalon Westergreen
Update devicetree bindings documentation to include msgdma
prefetcher and ptp bindings.
Signed-off-by: Dalon Westergreen
---
.../devicetree/bindings/net/alter
rwr8(u8 val, void __iomem *mac, size_t offs)
+{
+ void __iomem *paddr = (void __iomem *)((uintptr_t)mac + offs);
+
+ writeb(val, paddr);
+}
#endif /* __ALTERA_UTILS_H__*/
Acked-by: Thor Thayer
a = {
@@ -1677,6 +1681,7 @@ static const struct altera_dmaops altera_dtype_msgdma = {
.init_dma = msgdma_initialize,
.uninit_dma = msgdma_uninitialize,
.start_rxdma = msgdma_start_rxdma,
+ .start_txdma = NULL,
};
static const struct of_device_id altera_tse_id
)(struct altera_tse_private *priv);
+ void (*uninit_dma)(struct altera_tse_private *priv);
+ void (*start_rxdma)(struct altera_tse_private *priv);
};
/* This structure is private to each device.
Acked-by: Thor Thayer
x_ring_size = dma_tx_num;
ret = alloc_init_skbufs(priv);
if (ret) {
netdev_err(dev, "DMA descriptors initialization failed\n");
Acked-by: Thor Thayer
if (ret)
+ goto out;
skb_tx_timestamp(skb);
Acked-by: Thor Thayer
From: Thor Thayer
Vince has moved to a different role. Replace him as Altera
TSE maintainer.
Signed-off-by: Thor Thayer
Acked-by: Vince Bridgers
Acked-by: Alan Tull
---
v2 Include netdev and David Miller
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
From: Thor Thayer
Ping problems with packets > 8191 as shown:
PING 192.168.1.99 (192.168.1.99) 8150(8178) bytes of data.
8158 bytes from 192.168.1.99: icmp_seq=1 ttl=64 time=0.669 ms
wrong data byte 8144 should be 0xd0 but was 0x0
1610 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
Hi,
I'm running into a weird issue at the DMA boundary for large packets
(>8192) that I can't explain. I'm hoping someone here has an idea on
why I'm seeing this issue.
This is the Synopsys DesignWare Ethernet GMAC core (3.74) using the
stmmac driver found at drivers/net/ethernet/stmicro/st
From: Thor Thayer
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
in the Linux kernel modified the register dump to store the DMA registers
at the DMA register offset (0x1000) but ethtool (stmmac.c) looks for the
DMA registers after the MAC registers which is
From: Thor Thayer
This patch adds macros for the number of registers to
loop through to make the code easier to read.
Signed-off-by: Thor Thayer
---
v2 New commit. Add macros for number of registers.
v3 Only add macros - remove DMA indexing.
---
stmmac.c | 10 +++---
1 file changed, 7
From: Thor Thayer
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer
Acked-by: Giuseppe Cavallaro
---
v2 Modify for MACRO changes and add Acked-by
v3 No change
---
stmmac.c | 2 +-
1 file
On 06/28/2017 10:13 AM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
in the Linux kernel modified the register dump to store the DMA registers
at the DMA register offset (0x1000) but ethtool (stmmac.c)
From: Thor Thayer
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer
Acked-by: Giuseppe Cavallaro
---
v2 Modify for MACRO changes and add Acked-by
---
stmmac.c | 2 +-
1 file changed, 1
From: Thor Thayer
1. The DMA register dump structure changed which requires this
change to the indexing of the DMA registers.
2. Also dump the DMA HW Feature Register.
3. V2 also adds macros for the number of registers.
Thor Thayer (3):
ethtool: stmmac: Fix Designware ethtool register dump
From: Thor Thayer
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
in the Linux kernel modified the register dump to store the DMA registers
at the DMA register offset (0x1000) but ethtool (stmmac.c) looks for the
DMA registers after the MAC registers which is
From: Thor Thayer
This patch adds macros for the number of registers to
loop through to make the code easier to read.
Signed-off-by: Thor Thayer
---
v2 New commit. Add macros for number of registers.
---
stmmac.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a
On 06/28/2017 04:03 AM, Giuseppe CAVALLARO wrote:
On 6/27/2017 11:51 PM, thor.tha...@linux.intel.com wrote:
From: Thor Thayer
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer
---
stmmac.c
From: Thor Thayer
Version 3.70a of the Designware has additional DMA registers so
add those to the ethtool DMA Register dump.
Offset 9 - Receive Interrupt Watchdog Timer Register
Offset 10 - AXI Bus Mode Register
Offset 11 - AHB or AXI Status Register
Offset 22 - HW Feature Register
Signed-off
From: Thor Thayer
This patch adds the DMA HW Feature Register which is at the end
of the DMA registers and is documented in Version 3.70a.
Signed-off-by: Thor Thayer
---
stmmac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/stmmac.c b/stmmac.c
index e1bb291..7d7bebd
From: Thor Thayer
The commit fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
modified the register dump to store the DMA registers at the DMA register
offset (0x1000) but ethtool (stmmac.c) looks for the DMA registers after
the MAC registers which is offset 12.
This patc
From: Thor Thayer
The DMA register dump structure changed which requires this
change to the indexing of the DMA registers.
Also dump the DMA HW Feature Register.
Thor Thayer (2):
ethtool: stmmac: Fix Designware ethtool register dump
ethtool: stmmac: Add DMA HW Feature Register
stmmac.c
From: Thor Thayer
Fix NETDEV WATCHDOG timeout on startup by adding missing register
writes that properly setup SGMII.
Signed-off-by: Thor Thayer
---
drivers/net/ethernet/stmicro/stmmac/altr_tse_pcs.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet
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