left to be dealt with.
The second patch implements the MQPrio offloading for the receive path.
Changes in V2 :
- Add a Fixes tag for the first patch
- Fix some warnings and the xmas tree in the second patch
Thanks,
Maxime
Maxime Chevallier (2):
net: mvneta: Remove per-cpu queue mapping for A
Implement a basic MQPrio support, inserting rules in RX that translate
the TC to prio mapping into vlan prio to queues.
The TX logic stays the same as when we don't offload the qdisc.
Signed-off-by: Maxime Chevallier
---
V2 : Fixed the reverse xmas tree, as per Andrew's review.
the CPUs in
the system, both in the init path and in the cpu_hotplug path.
Fixes: 2636ac3cc2b4 ("net: mvneta: Add network support for Armada 3700 SoC")
Signed-off-by: Maxime Chevallier
---
V2: Added Fixes tag, as per Pali's review
drivers/net/ethernet/marvell/mvneta.c | 9 -
Hi Andrew,
On Sat, 13 Feb 2021 20:45:25 +0100
Andrew Lunn wrote:
>On Fri, Feb 12, 2021 at 04:12:20PM +0100, Maxime Chevallier wrote:
>> +static void mvneta_setup_rx_prio_map(struct mvneta_port *pp)
>> +{
>> +int i;
>> +u32 val = 0;
>
>Hi Maxime
>
arking
>this commit with Fixes line? E.g.:
>
>Fixes: 2636ac3cc2b4 ("net: mvneta: Add network support for Armada 3700
> SoC")
Yes you're correct, I'll add that to the V2 !
Thanks for the review,
Maxime
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
the CPUs in
the system, both in the init path and in the cpu_hotplug path.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvneta.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c
b/drivers/net/ethernet/marvell
Implement a basic MQPrio support, inserting rules in RX that translate
the TC to prio mapping into vlan prio to queues.
The TX logic stays the same as when we don't offload the qdisc.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvneta.c | 65 +
ements the MQPrio offloading for the receive path.
Thanks !
Maxime
Maxime Chevallier (2):
net: mvneta: Remove per-cpu queue mapping for Armada 3700
net: mvneta: Implement mqprio support
drivers/net/ethernet/marvell/mvneta.c | 74 ++-
1 file changed, 73 insertions(+),
Hi Russell, Andrew,
On Fri, 20 Nov 2020 14:55:17 +0100
Andrew Lunn wrote:
>On Fri, Nov 20, 2020 at 10:25:38AM +, Russell King - ARM Linux admin wrote:
>> On Fri, Nov 20, 2020 at 10:36:01AM +0100, Maxime Chevallier wrote:
>> > So maybe we could be a bit more generic, wi
Hi Tobias,
On Fri, 20 Nov 2020 01:11:12 +0100
Tobias Waldekranz wrote:
>On Thu, Nov 19, 2020 at 23:16, Russell King - ARM Linux admin
> wrote:
>> On Thu, Nov 19, 2020 at 11:43:39PM +0100, Tobias Waldekranz wrote:
>>> On Thu, Nov 19, 2020 at 16:24, Maxime Chevallier
the MUX in the MAC?
No, it's my schematic that is misleading in that case :) The 2
ports are independent of each other. There isn't any configuration on
the MAC part for that setup.
Thanks,
Maxime
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hello Russell,
On Thu, 19 Nov 2020 14:55:00 +
Russell King - ARM Linux admin wrote:
>On Thu, Nov 19, 2020 at 03:22:46PM +0100, Maxime Chevallier wrote:
>> Hello everyone,
>>
>> I'm reaching out to discuss an issue I'm currently having, while working
>>
Hello everyone,
I'm reaching out to discuss an issue I'm currently having, while working
on a Marvell 88E1543 PHY.
This PHY is very similar to the 88E1545 we already support upstream, but
with an added "dual-port mode" feature that I'm currently using in a
project, and that might be interesting t
gt;@@ -5107,7 +5137,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
> dev->netdev_ops = &mvpp2_netdev_ops;
> dev->ethtool_ops = &mvpp2_eth_tool_ops;
>
>- port = netdev_priv(dev);
> port->dev = dev;
> port->fwnode = port_fwnode;
> port->has_phy = !!of_find_property(port_node, "phy", NULL);
>@@ -5144,7 +5173,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
>
> port->of_node = port_node;
> port->phy_interface = phy_mode;
>- port->comphy = comphy;
>
> if (priv->hw_version == MVPP21) {
> port->base = devm_platform_ioremap_resource(pdev, 2 + id);
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hello Nathan,
On Thu, 13 Jun 2019 10:53:05 -0700
Nathan Huckleberry wrote:
>Hey all,
>
>I'm looking into cleaning up ignored warnings in the kernel so we can
>remove compiler flags to ignore warnings.
>
>There's an unused variable 'mvpp2_dbgfs_prs_pmap_fops' in
>mvpp2_debugfs.c. It looks like th
p2, is
there a reason for that ?
Other than that, for the mvpp2 part,
Reviewed-by: Maxime Chevallier
Tested-by: Maxime Chevallier
Thanks,
Maxime
0, who both have the same
register at the same location, at are potentially subject to the same
issue.
Tested-by: Maxime Chevallier
Thanks,
Maxime
Hello Ioana,
On Thu, 23 May 2019 01:20:36 +
Ioana Ciornei wrote:
>Following two separate discussion threads in:
> https://www.spinics.net/lists/netdev/msg569087.html
>and:
> https://www.spinics.net/lists/netdev/msg570450.html
>
>PHYLINK was reworked in order to add a new "raw" interface, a
Hi everyone,
On Wed, 15 May 2019 09:09:26 -0700
Florian Fainelli wrote:
>On 5/15/19 7:02 AM, Maxime Chevallier wrote:
>> Hi Andrew,
>>
>> On Wed, 15 May 2019 15:27:01 +0200
>> Andrew Lunn wrote:
>>
>>> I think you are getting your terminology wron
Hi Andrew,
On Wed, 15 May 2019 15:27:01 +0200
Andrew Lunn wrote:
>I think you are getting your terminology wrong. 'master' is eth0 in
>the example you gave above. CPU and DSA ports don't have netdev
>structures, and so any PHY used with them is not corrected to a
>netdev.
Ah yes sorry, I'm stil
Hello everyone,
I'm working on a setup where I have a 88e6390X DSA switch connected to
a CPU (an armada 8040) with 2500BaseX and RXAUI interfaces (we only use
one at a time).
I'm facing a limitation with the current way to represent that link,
where we use a fixed-link description in the CPU port
Hi Yanko,
>On Tue, 14 May 2019 10:29:31 +0300
>Yanko Kaneti wrote:
>
>> Hello,
>>
>> I am trying to get some Fedora working on the MACCHIATObin SingleShot
>> and I am getting an OOPS on what seems to be the first received packet
>> on the gigabit port.
>>
>> I've tried both 5.0.x stable and 5.1
on offload support")
Reported-by: Jakub Kicinski
Acked-by: Jakub Kicinski
Signed-off-by: Maxime Chevallier
---
V2: Rebased on latest -net, added Jakub's Ack, gave more details in the
commit log about not adding the flag in hw_features.
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
Hi Petr,
On Mon, 6 May 2019 10:32:07 +0200
Petr Štetiar wrote:
>David Miller [2019-05-05 21:47:27]:
>
>Hi David,
>
>> Series applied, thank you.
>
>I did probably something terribly wrong, but patch "[PATCH v4 05/10] net:
>ethernet: support of_get_mac_address new ERR_PTR error" has not reache
the "steer to rxq" action.
Signed-off-by: Maxime Chevallier
---
V2: - Re-arranged struct mvpp2_rfs_rule to minimize gaps on 64 bits systems,
as suggested by David.
- Fixed a smatch error indicating a possible out-of-bound array access
when accessing the internal lis
ports but the 9 and 10, and because modes supported by 6390
ports 9 and 10 are a subset of those supported on 6390X.
This was tested on 6390X using RXAUI mode.
Fixes: 364e9d7776a3 ("net: dsa: mv88e6xxx: Power on/off SERDES on cmode change")
Signed-off-by: Maxime Chevallier
---
drive
The genphy_c45_pma_read_abilities helper now sets the Autoneg ability
in phydev->supported according to what the AN MMD reports.
We therefore don't need to manually do that in mv3310_get_features().
Signed-off-by: Maxime Chevallier
Suggested-by: Heiner Kallweit
---
drivers
Contrary to the 3310, the 2110 PHY correctly reports it's 2.5G/5G
abilities. We can therefore use the genphy_c45_pma_read_abilities helper
to build the list of features.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
, since it doesn't have the
issue with the wrong abilities being reported.
Maxime Chevallier (2):
net: phy: marvell10g: Let genphy_c45_pma_read_abilities set Aneg bit
net: phy: marvell10g: Use the generic C45 helper to read the 2110
features
drivers/net/phy/marvell10g.c | 12 +-
really is that the -net patch
also masks the 2.5/5G Fast Retrain abilities, but this should make no
difference given that 2.5/5G are masked-out in both cases.
I'm sorry for the confusion, I wasn't sure how to deal with such a
scenario.
Thanks,
Maxime
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
The PHY ID corresponding to the 88X3310 is also used for other PHYs in
the same family, such as the 88E2010. Use a #define for the PHY id, that
ignores the last nibble.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 4 ++--
include/linux/marvell_phy.h | 1 +
2 files
ue as the 88x3310 regarding 2.5/5G
abilities, and correctly follows the 802.3bz standard to list the
supported abilities.
Signed-off-by: Maxime Chevallier
Suggested-by: Antoine Tenart
---
drivers/net/phy/marvell10g.c | 13 +
include/linux/marvell_phy.h | 1 +
2 files changed, 14 inser
formatting issue in patch 01, rebased.
Maxime Chevallier (7):
net: phy: marvell10g: Use get_features to get the PHY abilities
net: phy: marvell10g: Use linkmode_set_bit helper instead of __set_bit
net: phy: marvell10g: Use 2500BASEX when using 2.5GBASET
net: phy: marvell10g: Use a #define f
1.11.14 bit set, as it should.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9c0b8f16cec5..8f354c3f3876 100644
--- a/driv
Cosmetic patch making use of helpers dedicated to linkmodes handling.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 89920b10d75b
adding autoneg ability based on what's reported by the AN
MMD.
.config_init is still used to validate the interface_mode.
Signed-off-by: Maxime Chevallier
---
V2: Added missing blank line
drivers/net/phy/marvell10g.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --
The PPv2 controller is able to support 2.5G speeds, allowing to use
2.5GBASET in conjunction with PHYs that use 2500BASEX as their MII
interface when using this mode.
Signed-off-by: Maxime Chevallier
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 1 +
1 file
x27;t supported by any MAC for now.
This was tested with :
- The 88X3310, which is on the MacchiatoBin
- The 88E2010, an Alaska PHY that has no fiber interfaces, and is
limited to 5G maximum speed.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 26 +++
On Fri, 22 Feb 2019 19:42:29 +0100
Heiner Kallweit wrote:
>After my just submitted patch to include the aneg capability checking in
>genphy_c45_pma_read_abilities() function mv3310_get_features() isn't
>needed any longer and can be replaced with the generic one.
I'll still need it to handle the
;*phydev)
This makes the helper not reading PMA-only registers, so the naming
isn't really relevant anymore, but that's a small detail.
Other than that,
Reviewed-by: Maxime Chevallier
Thanks,
Maxime
: 20b2af32ff3f ("net: phy: add Marvell Alaska X 88X3310 10Gigabit PHY
support")
Signed-off-by: Maxime Chevallier
Reported-by: Russell King
---
Dave,
This patch will conflict when merging net into net-next, and is actually
not needed there. In net-next, this issue is fixed by the recent wo
Hello Russell,
On Thu, 21 Feb 2019 10:22:15 +
Russell King - ARM Linux admin wrote:
>> +return 0;
>> +}
>> +
>> +static int mv3310_get_features(struct phy_device *phydev)
>> +{
>> +int ret, val;
>
>Please try to keep the formatting/style consistent in the file you are
>editing. A
x27;t supported by any MAC for now.
This was tested with :
- The 88X3310, which is on the MacchiatoBin
- The 88E2010, an Alaska PHY that has no fiber interfaces, and is
limited to 5G maximum speed.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 26 +++
1.11.14 bit set, as it should.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 9323bcf15dbd..c48669d50653 100644
--- a/driv
adding autoneg ability based on what's reported by the AN
MMD.
.config_init is still used to validate the interface_mode.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/phy/marvell10
ue as the 88x3310 regarding 2.5/5G
abilities, and correctly follows the 802.3bz standard to list the
supported abilities.
Signed-off-by: Maxime Chevallier
Suggested-by: Antoine Tenart
---
drivers/net/phy/marvell10g.c | 13 +
include/linux/marvell_phy.h | 1 +
2 files changed, 14 inser
Cosmetic patch making use of helpers dedicated to linkmodes handling.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 65ef469adf58
The PHY ID corresponding to the 88X3310 is also used for other PHYs in
the same family, such as the 88E2010. Use a #define for the PHY id, that
ignores the last nibble.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 4 ++--
include/linux/marvell_phy.h | 1 +
2 files
g the correct helper to set a linkmode bit and adding macros for the
PHY ids.
We also add support for the 88E2110 PHY, which doesn't require the
quirk, and support for 2500BaseT in the PPv2 driver, in order to have a
fully working setup on the MacchiatoBin board.
Maxime Chevallier (7):
The PPv2 controller is able to support 2.5G speeds, allowing to use
2.5GBASET in conjunction with PHYs that use 2500BASEX as their MII
interface when using this mode.
Signed-off-by: Maxime Chevallier
Reviewed-by: Andrew Lunn
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 1 +
1 file
Hello Russell,
On Thu, 7 Feb 2019 23:48:24 +
Russell King - ARM Linux admin wrote:
>On Thu, Feb 07, 2019 at 10:49:36AM +0100, Maxime Chevallier wrote:
>> The Marvell Alaska family of PHYs supports 2.5GBaseT and 5GBaseT modes,
>> as defined in the 802.3bz specification.
>&
The PHY core expects PHY drivers not to set Pause and Asym_Pause bits,
unless the driver only wants to specify one of them due to HW
limitation. In the case of the Marvell10g driver, we don't need to set
them.
Signed-off-by: Maxime Chevallier
Suggested-by: Andrew Lunn
---
drivers/ne
When setting a PHY's max speed using either the max-speed DT property
or ethtool, we should mask-out all non-compatible modes according to the
settings table, instead of just the 10/100BASET modes.
Signed-off-by: Maxime Chevallier
Suggested-by: Russell King
Reviewed-by: Andrew
Since of_set_phy_supported was moved to phy-core.c, we can also move
of_set_phy_eee_broken to the same location, so that we have all OF
functions in the same place.
This patch doesn't intend to introduce any change in behaviour.
Signed-off-by: Maxime Chevallier
Reviewed-by: Andrew
/20190118152352.26417-1-maxime.chevall...@bootlin.com/
[2] :
https://lore.kernel.org/netdev/20190207094939.27369-1-maxime.chevall...@bootlin.com/
[3] :
https://lore.kernel.org/netdev/81c340ea-54b0-1abf-94af-b8dc4ee83...@gmail.com/
Maxime Chevallier (4):
net: phy: Mask-out non-compatible modes when setting the
g and uses it to introduce the genphy_c45_pma_read_abilities
function.
Only PMA modes are read, it's still up to the caller to set the Pause
parameters.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 78
drivers/net/phy/phy-c45
-off-by: Maxime Chevallier
---
drivers/net/phy/phy-c45.c | 37 +
include/uapi/linux/mdio.h | 16
2 files changed, 53 insertions(+)
diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
index 6f028de4dae1..7af5fa81daf6 100644
--- a
;consistency through the driver.
>
>Signed-off-by: Russell King
Reviewed-by: Maxime Chevallier
Thanks,
Maxime
Hello Russell,
On Mon, 11 Feb 2019 10:23:10 +
Russell King wrote:
>Add a mvpp2_is_xlg() helper to identify whether the interface mode
>should be using the XLGMAC rather than the GMAC.
>
>Signed-off-by: Russell King
Reviewed-by: Maxime Chevallier
Thanks,
Maxime
Hello Heiner,
>Hi Maxime,
>
>Andrew and me are working on Aquantia PHY support and he handed over
>to me a patch series which includes parts of the first version of your
>series. Having said that I'm especially interested in your patches
>5 and 6. Because your series is somewhat bigger and there a
Hello Andrew,
On Thu, 7 Feb 2019 15:09:39 +0100
Andrew Lunn wrote:
>On Thu, Feb 07, 2019 at 10:49:33AM +0100, Maxime Chevallier wrote:
>> PHY advertised and supported linkmodes contain both specific modes such
>> as 1000BASET Half/Full and generic ones such as TP that represen
Hello Andrew,
On Thu, 7 Feb 2019 14:48:07 +0100
Andrew Lunn wrote:
>On Thu, Feb 07, 2019 at 10:49:30AM +0100, Maxime Chevallier wrote:
>> We want to be able to update a PHY's supported list in the config_init
>> callback, so move the Pause parameters settings from phydr
Hello everyone,
On Thu, 7 Feb 2019 10:49:30 +0100
Maxime Chevallier wrote:
>We want to be able to update a PHY's supported list in the config_init
>callback, so move the Pause parameters settings from phydrv->features
>after calling config_init to make sure these
We want to be able to update a PHY's supported list in the config_init
callback, so move the Pause parameters settings from phydrv->features
after calling config_init to make sure these parameters aren't
overwritten.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/phy_
kmode_mod_bit to make sure we mask-out unsupported modes.
- In Patch 8, we manually check for the PMA device id to see if we have
to use a quirk when reading the 2.5G/5G Extended Abilities
Maxime Chevallier (10):
net: phy: Update PHY linkmodes after config_init
net: phy: Mask-out non-compati
ue as the 88x3310 regarding 2.5/5G
abilities, and correctly follows the 802.3bz standard to list the
supported abilities.
Signed-off-by: Maxime Chevallier
Suggested-by: Antoine Tenart
---
V1 -> V2: Use a #define for the PHY ID, since we also do that for the
3310. Removed the mv2110_con
The PPv2 controller is able to support 2.5G speeds, allowing to use
2.5GBASET in conjunction with PHYs that use 2500BASEX as their MII
interface when using this mode.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 1 +
1 file changed, 1 insertion(+)
diff
g and uses it to introduce the genphy_c45_pma_read_abilities
function.
Only PMA modes are read, it's still up to the caller to set the Pause
parameters.
Signed-off-by: Maxime Chevallier
---
V1 -> V2: The Pause parameters setting stays in marvell10g. Make use of
linkmode_mod_bit
Since of_set_phy_supported was moved to phy-core.c, we can also move
of_set_phy_eee_broken to the same location, so that we have all OF
functions in the same place.
This patch doesn't intend to introduce any change in behaviour.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/phy-c
this
mode isn't supported by any MAC for now.
This was tested with :
- The 88X3310, which is on the MacchiatoBin
- The 88E2010, an Alaska PHY that has no fiber interfaces, and is
limited to 5G maximum speed.
Signed-off-by: Maxime Chevallier
---
V1 -> V2: Use a #define for the 88X3310
-off-by: Maxime Chevallier
---
V1 -> V2: Merged in code for reading 2.5G/5G abilities.
drivers/net/phy/phy-c45.c| 37
drivers/net/phy/phy_device.c | 2 ++
include/uapi/linux/mdio.h| 16
3 files changed, 55 insertions(+)
diff --gi
specific modes it corresponds to is present in the list.
The 'TP' bit is set whenever there's a BaseT linkmode in
phydev->supported.
The 'FIBRE' bit is set for BaseL, BaseS and BaseE linkmodes.
Finally, the 'Backplane' is set whenever a BaseK mode is suppor
1.11.14 bit set, as it should.
Signed-off-by: Maxime Chevallier
---
V1 -> V2: Use the PMA device id to identify which devices need this
quirk, based on Andrew's idea.
drivers/net/phy/marvell10g.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/
When setting a PHY's max speed using either the max-speed DT property
or ethtool, we should mask-out all non-compatible modes according to the
settings table, instead of just the 10/100BASET modes.
Signed-off-by: Maxime Chevallier
Suggested-by: Russell King
---
drivers/net/phy/phy-c
Hello Russell,
On Wed, 06 Feb 2019 11:35:07 +
Russell King wrote:
>+ if (pp->comphy) {
>+ enum phy_mode mode = PHY_MODE_INVALID;
>+
>+ switch (state->interface) {
>+ case PHY_INTERFACE_MODE_SGMII:
>+ case PHY_INTERFACE_MODE_1000BASEX:
Hello Russell,
On Mon, 21 Jan 2019 13:00:30 +
Russell King - ARM Linux admin wrote:
>On Mon, Jan 21, 2019 at 01:29:45PM +0100, Maxime Chevallier wrote:
>> Hello Russell,
>>
>> On Mon, 21 Jan 2019 10:52:06 +
>> Russell King - ARM Linux admin wrote:
>>
e seems to be a
lot of quirks and complex cases that we need to take into account, so
I'll let you decide :)
>Heiner, you know this code better than anybody. What do you think?
>
> Andrew
Thanks for the feedback,
Maxime
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hello Andrew,
On Sun, 20 Jan 2019 19:51:07 +0100
Andrew Lunn wrote:
>On Fri, Jan 18, 2019 at 04:23:46PM +0100, Maxime Chevallier wrote:
>> Marvell 10G PHY driver has a generic way of initializing the supported
>> link modes by reading the PHY's C45 PMA abilities. This ca
Hello Russell,
On Mon, 21 Jan 2019 10:52:06 +
Russell King - ARM Linux admin wrote:
>On Mon, Jan 21, 2019 at 11:35:31AM +0100, Maxime Chevallier wrote:
>> Hello Andrew,
>>
>> On Sun, 20 Jan 2019 20:08:09 +0100
>> Andrew Lunn wrote:
>>
>> &g
Hello Andrew,
On Sun, 20 Jan 2019 20:08:09 +0100
Andrew Lunn wrote:
>On Fri, Jan 18, 2019 at 04:23:50PM +0100, Maxime Chevallier wrote:
>> As per 802.3bz, if bit 14 of (1.11) "PMA Extended Abilities" indicates
>> whether or not we should read register (1.21) "2.5
g and uses it to introduce the genphy_c45_read_abilities
function.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 80 ++
drivers/net/phy/phy-c45.c| 96
include/linux/phy.h | 1 +
3 files changed
nect to the
MAC in that case.
Thanks to Andrew for doing the rework of the link_mode representation
this series depends on.
Maxime Chevallier (7):
net: phy: Extract genphy_c45_read_abilities from marvell10g
net: phy: Add generic support for 2.5GBaseT and 5GBaseT
net: phy: Read 2.5G and 5G ext
this
mode isn't supported by any MAC for now.
This was tested with :
- The 88X3310, which is on the MacchiatoBin
- The 88E2010, an Alaska PHY that has no fiber interfaces, and is
limited to 5G maximum speed.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/ma
1.11.14 bit set, as it should.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/marvell10g.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f45ddf3bc138..0a35bf0fac47 100644
--- a/driv
ue as the 88x3310 regarding 2.5/5G
abilities, and correctly follows the 802.3bz standard to list the
supported abilities.
Signed-off-by: Maxime Chevallier
Suggested-by: Antoine Tenart
---
drivers/net/phy/marvell10g.c | 37
1 file changed, 37 insertions(+)
diff
The PPv2 controller is able to support 2.5G speeds, allowing to use
2.5GBASET in conjunction with PHYs that use 2500BASEX as their MII
interface when using this mode.
Signed-off-by: Maxime Chevallier
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 1 +
1 file changed, 1 insertion(+)
diff
bove-mentionned 1.21 register should be taken
into account.
This commit adds that logic into the genphy_c45_read_abilities function.
Signed-off-by: Maxime Chevallier
---
drivers/net/phy/phy-c45.c | 14 ++
include/uapi/linux/mdio.h | 6 ++
2 files changed, 20 insertions(+)
diff --g
-off-by: Maxime Chevallier
---
drivers/net/phy/phy-c45.c | 22 ++
include/uapi/linux/mdio.h | 10 ++
2 files changed, 32 insertions(+)
diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
index 31806b432734..61ca4f89e94a 100644
--- a/drivers/net/phy/phy-c45
t fine.
Thanks,
Tested-by: Maxime Chevallier
>Signed-off-by: Grygorii Strashko
>---
> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 19 +-
> drivers/phy/marvell/phy-mvebu-cp110-comphy.c| 83 ++---
> 2 files changed, 48 insertions(+), 54 deletions(-)
&g
Hi Russell,
On Mon, 12 Nov 2018 12:31:07 +
Russell King wrote:
Maybe missing a commit log ?
Otherwise,
Tested-by: Maxime Chevallier
>Signed-off-by: Russell King
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hi Russell,
On Mon, 12 Nov 2018 12:31:12 +
Russell King wrote:
>Add the comphy settings for the Ethernet interfaces.
Tested-by: Maxime Chevallier
>Signed-off-by: Russell King
Hello Russell,
On Mon, 12 Nov 2018 12:29:33 +
Russell King - ARM Linux wrote:
>Hi,
>
>This series adds support for dynamically switching between 1Gbps
>and 2.5Gbps networking for the Marvell Armada 38x SoCs, tested on
>Armada 388 on the Clearfog platform.
I've performed some tests on my sid
Hi Russell,
On Mon, 12 Nov 2018 12:30:57 +
Russell King wrote:
>Add the DT description for the Armada 38x common phy.
Tested-by: Maxime Chevallier
>Signed-off-by: Russell King
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
.
Tested-by: Maxime Chevallier
>Signed-off-by: Russell King
--
Maxime Chevallier, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
Hi Andrew,
On Fri, 14 Sep 2018 23:38:48 +0200
Andrew Lunn wrote:
>These patches contain some further cleanup and helpers, and the first
>real patch towards using linkmode bitmaps in phylink.
>
>It is RFC because i don't like patch #7 and maybe somebody has a
>better idea how to do this. Ideally,
On Fri, 14 Sep 2018 23:38:53 +0200
Andrew Lunn wrote:
>Add helpers which take a linkmode rather than a u32 ethtool for
>advertising settings.
>
>Signed-off-by: Andrew Lunn
Reviewed-by: Maxime Chevallier
On Fri, 14 Sep 2018 23:38:52 +0200
Andrew Lunn wrote:
>Add a helper to convert the local advertising to an LCL capabilities,
>which is then used to resolve pause flow control settings.
>
>Signed-off-by: Andrew Lunn
Reviewed-by: Maxime Chevallier
register value to a linkmode.
>
>Signed-off-by: Andrew Lunn
Reviewed-by: Maxime Chevallier
On Fri, 14 Sep 2018 23:38:50 +0200
Andrew Lunn wrote:
>Not all new style LINK_MODE bits can be converted into old style
>SUPPORTED bits. We need to warn when such a conversion is attempted.
>Add a helper for this.
>
>Signed-off-by: Andrew Lunn
Reviewed-by: Maxime Chevallier
On Fri, 14 Sep 2018 23:38:49 +0200
Andrew Lunn wrote:
>phylink has some useful helpers to working with linkmode bitmaps.
>Move them to there own header so other code can use them.
>
>Signed-off-by: Andrew Lunn
Reviewed-by: Maxime Chevallier
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