Thanks Fabio.
On 10/21/2016 06:43 AM, Fabio Estevam wrote:
> Hi Eric,
>
> On Fri, Oct 21, 2016 at 11:39 AM, Eric Nelson wrote:
>
>> Reading the i.MX28 reference manual, it appears that this SoC doesn't
>> have the RACC bit, and I missed removal of the FEC_QUIRK_HA
Hi Henri,
On 10/21/2016 06:39 AM, Eric Nelson wrote:
> Hi Henri,
>
> On 10/21/2016 02:19 AM, Henri Roosen wrote:
>> Hi,
>>
>> Unfortunately commit-3ac72b7b63d5 "net: fec: align IP header in
>> hardware" breaks networking on an iMX28 system.
>>
Hi Henri,
On 10/21/2016 02:19 AM, Henri Roosen wrote:
> Hi,
>
> Unfortunately commit-3ac72b7b63d5 "net: fec: align IP header in
> hardware" breaks networking on an iMX28 system.
>
> The commit seems valid for iMX6, where it is tested okay and solves the
> unaligned accesses.
>
> On iMX28 I stil
Hi Russell,
On 10/01/2016 09:52 PM, Russell King - ARM Linux wrote:
> On Fri, Sep 30, 2016 at 07:16:12AM -0700, Eric Nelson wrote:
>> On ARM, the CPU can't handle misaligned memory cycles without
>> taking an alignment fault and NET_IP_ALIGN is set to 2.
>
> Let'
Hi David,
On 09/30/2016 06:49 AM, David Laight wrote:
> From: Eric Nelson
>> Sent: 30 September 2016 14:27
>> Thanks for the feedback David,
>>
>> On 09/29/2016 04:07 AM, David Laight wrote:
>>> From: Eric Nelson
>>>> Sent: 28 September 2016 18:15
Thanks for the feedback David,
On 09/29/2016 04:07 AM, David Laight wrote:
> From: Eric Nelson
>> Sent: 28 September 2016 18:15
>> On 09/28/2016 09:42 AM, David Laight wrote:
>>> From: Eric Nelson
>>>> Sent: 26 September 2016 19:40
>>>> Hi David
Thanks Russell,
On 09/28/2016 10:25 AM, Russell King - ARM Linux wrote:
> On Wed, Sep 28, 2016 at 10:14:52AM -0700, Eric Nelson wrote:
>> Thanks David,
>>
>> On 09/28/2016 09:42 AM, David Laight wrote:
>>> From reading this it seems that the effect of FEC_RACC_SHIF
Thanks David,
On 09/28/2016 09:42 AM, David Laight wrote:
> From: Eric Nelson
>> Sent: 26 September 2016 19:40
>> Hi David,
>>
>> On 09/26/2016 02:26 AM, David Laight wrote:
>>> From: Eric Nelson
>>>> Sent: 24 September 2016 15:42
>>>> T
Hi David,
On 09/26/2016 02:26 AM, David Laight wrote:
> From: Eric Nelson
>> Sent: 24 September 2016 15:42
>> The FEC receive accelerator (RACC) supports shifting the data payload of
>> received packets by 16-bits, which aligns the payload (IP header) on a
>> 4-byte
On 09/24/2016 08:09 AM, Andy Duan wrote:
> From: Eric Nelson Sent: Saturday, September 24, 2016 10:42
> PM
>> To: netdev@vger.kernel.org
>> Cc: li...@arm.linux.org.uk; and...@lunn.ch; Andy Duan
>> ; ota...@ossystems.com.br;
>> eduma...@google.com; troy.ki
.uk/cgit/linux-arm.git/commit/?id=70d8a8a
Signed-off-by: Eric Nelson
---
drivers/net/ethernet/freescale/fec_main.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/fec_main.c
b/drivers/net/ethernet/freescale/fec_main.c
index 0219e79.
According to the i.MX27 reference manual, this SoC does not have support
for the receive accelerator (RACC) register at offset 0x1C4.
http://cache.nxp.com/files/32bit/doc/ref_manual/MCIMX27RM.pdf
Signed-off-by: Eric Nelson
---
drivers/net/ethernet/freescale/fec_main.c | 2 +-
1 file
According to the i.MX25 reference manual, this SoC does not have support
for the receive accelerator (RACC) register at offset 0x1C4.
http://www.nxp.com/files/dsp/doc/ref_manual/IMX25RM.pdf
Signed-off-by: Eric Nelson
---
drivers/net/ethernet/freescale/fec_main.c | 2 +-
1 file changed, 1
aults during a 100MiB transfer using
wget.
Testing on an i.MX6Q (SABRE Lite) board on net-next (4.8.0-rc7) showed
a much more modest improvement from 10's of faults, and it's not clear
why that's the case.
Eric Nelson (3):
net: fec: remove QUIRK_HAS_RACC from i.mx25
net: fec: r
Hi David,
On 09/23/2016 07:43 PM, David Miller wrote:
> From: Eric Nelson
> Date: Fri, 23 Sep 2016 10:33:29 -0700
>
>> Since the hardware requires longword alignment for its' DMA transfers,
>> aligning the IP header will require a memcpy, right?
>
> I wish h
Thanks Russell,
On 09/23/2016 11:37 AM, Russell King - ARM Linux wrote:
> On Fri, Sep 23, 2016 at 11:26:18AM -0700, Eric Nelson wrote:
>> So the question is: should we just live with this and acknowledge a
>> performance penalty of bad alignment or do something about it?
>
Thanks Russell,
On 09/23/2016 11:30 AM, Russell King - ARM Linux wrote:
> On Fri, Sep 23, 2016 at 08:13:01PM +0200, Andrew Lunn wrote:
>>> Since the hardware requires longword alignment for its' DMA transfers,
>>> aligning the IP header will require a memcpy, right?
>>
>> The vf610 FEC has an SHIF
Thanks Andrew.
On 09/23/2016 11:13 AM, Andrew Lunn wrote:
>> Since the hardware requires longword alignment for its' DMA transfers,
>> aligning the IP header will require a memcpy, right?
>
> The vf610 FEC has an SHIFT16 bit in register ENETx_TACC, which inserts
> two padding bits on transmit. EN
Thanks Russell,
On 09/23/2016 10:37 AM, Russell King - ARM Linux wrote:
> On Fri, Sep 23, 2016 at 10:19:50AM -0700, Eric Nelson wrote:
>> Oddly, it does prevent the vast majority (90%+) of the alignment errors.
>>
>> I believe this is because the compiler is generating an ld
Hi Eric,
On 09/23/2016 10:19 AM, Eric Nelson wrote:
> Thanks Eric,
>
> On 09/23/2016 09:54 AM, Eric Dumazet wrote:
>> On Fri, Sep 23, 2016 at 9:43 AM, Eric Nelson wrote:
>>>
>>> Hello all,
>>>
>>> We're seeing alig
Thanks Eric,
On 09/23/2016 09:54 AM, Eric Dumazet wrote:
> On Fri, Sep 23, 2016 at 9:43 AM, Eric Nelson wrote:
>>
>> Hello all,
>>
>> We're seeing alignment issues from the ethernet stack on an i.MX6UL board:
>>
>>
>>
>> - id = ntohl(
et/lists/netdev/msg213166.htm
The immediate problem is addressed by just reading the id and frag_offs
fields in the iphdr structure as shown in this patch:
commit 98810abc911b1286a7e4a2ebdfbad66f12fae19d
Author: Eric Nelson
Date: Fri Sep 23 08:26:03 2016 -0700
net: ipv4: af_inet: don't
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