W dniu 2020-09-04 o 16:23, Andrew Lunn pisze:
On Fri, Sep 04, 2020 at 04:00:55PM +0200, Adam Rudziński wrote:
W dniu 2020-09-04 o 15:45, Andrew Lunn pisze:
Just a bunch of questions.
Actually, why is it necessary to have a full MDIO bus scan already during
probing peripherals?
That is the
W dniu 2020-09-04 o 15:45, Andrew Lunn pisze:
Just a bunch of questions.
Actually, why is it necessary to have a full MDIO bus scan already during
probing peripherals?
That is the Linux bus model. It does not matter what sort of bus it
is, PCI, USB, MDIO, etc. When the bus driver is loaded, the
W dniu 2020-09-04 o 06:04, Florian Fainelli pisze:
On 9/2/2020 9:39 PM, Florian Fainelli wrote:
Hi all,
This patch series takes care of enabling the Ethernet PHY clocks in
DT-based systems (we have no way to do it for ACPI, and ACPI would
likely keep all of this hardware enabled anyway).
P
W dniu 2020-09-03 o 21:35, Florian Fainelli pisze:
On 9/3/2020 12:21 PM, Adam Rudziński wrote:
W dniu 2020-09-03 o 19:17, Florian Fainelli pisze:
On 9/3/2020 10:13 AM, Adam Rudziński wrote:
W dniu 2020-09-03 o 17:21, Florian Fainelli pisze:
On 9/2/2020 11:00 PM, Adam Rudziński
W dniu 2020-09-03 o 19:17, Florian Fainelli pisze:
On 9/3/2020 10:13 AM, Adam Rudziński wrote:
W dniu 2020-09-03 o 17:21, Florian Fainelli pisze:
On 9/2/2020 11:00 PM, Adam Rudziński wrote:
W dniu 2020-09-03 o 04:13, Florian Fainelli pisze:
On 9/2/2020 3:20 PM, Andrew Lunn wrote
W dniu 2020-09-03 o 17:21, Florian Fainelli pisze:
On 9/2/2020 11:00 PM, Adam Rudziński wrote:
W dniu 2020-09-03 o 04:13, Florian Fainelli pisze:
On 9/2/2020 3:20 PM, Andrew Lunn wrote:
+ priv->clk = devm_clk_get_optional(&phydev->mdio.dev, "sw_gphy");
+
W dniu 2020-09-03 o 04:13, Florian Fainelli pisze:
On 9/2/2020 3:20 PM, Andrew Lunn wrote:
+ priv->clk = devm_clk_get_optional(&phydev->mdio.dev, "sw_gphy");
+ if (IS_ERR(priv->clk))
+ return PTR_ERR(priv->clk);
+
+ /* To get there, the mdiobus registration logic already enab
W dniu 2020-08-30 o 01:16, Andrew Lunn pisze:
I meant that with the split description of the mdio node the mdio bus for
use in the system would be selected almost automatically. Suppose that I can
do the device tree "my way":
&fec2 {
...
mdio { phy2 ... };
...
};
&fec1 {
...
mdio { phy1
W dniu 2020-08-29 o 18:00, Andrew Lunn pisze:
This is true assuming that the PHYs are always and forever connected to one
specific MDIO bus. This is probably reasonable. Although, in i.MX the MDIO
bus of FEC1 and FEC2 shares the pins.
In general, they do not. In fact, i don't see how that can wo
W dniu 2020-08-29 o 17:15, Andrew Lunn pisze:
The driver would be able to add the new PHYs to the shared MDIO bus by
calling of_mdiobus_register_children. Then the device tree looks like this,
which is more reasonable in my opinion:
&fec2 {
(...)
mdio {
(phy for fec2 here)
};
W dniu 2020-08-29 o 05:29, Florian Fainelli pisze:
On 8/28/2020 4:14 PM, Adam Rudziński wrote:
W dniu 2020-08-29 o 00:53, Andrew Lunn pisze:
On Sat, Aug 29, 2020 at 12:34:05AM +0200, Adam Rudziński wrote:
Hi Andrew.
W dniu 2020-08-29 o 00:28, Andrew Lunn pisze:
Hi Adam
If kernel has to
s an attachment to an
email)?
Best regards,
Adam
-----
Adam Rudziński
A.R.f.
http://arf.net.pl
W dniu 2020-08-29 o 00:53, Andrew Lunn pisze:
On Sat, Aug 29, 2020 at 12:34:05AM +0200, Adam Rudziński wrote:
Hi Andrew.
W dniu 2020-08-29 o 00:28, Andrew Lunn pisze:
Hi Adam
If kernel has to bring up two Ethernet interfaces, the processor has two
peripherals with functionality of MACs (in
Hi Andrew.
W dniu 2020-08-29 o 00:28, Andrew Lunn pisze:
Hi Adam
If kernel has to bring up two Ethernet interfaces, the processor has two
peripherals with functionality of MACs (in i.MX6ULL these are Fast Ethernet
Controllers, FECs), but uses a shared MDIO bus, then the kernel first probes
one
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