> Hmm, are you sure you need to convert
> "err" to the pointer, just to return true/false
> as the return value?
> How about still returning "err" itself?
In this case i need to reserve some value for
"err" as success, because both 0 and negative
values are passed to caller when this function
retu
On Fri, Jan 08, 2021 at 11:21:13PM +0100, Daniel Borkmann wrote:
> On 1/7/21 3:16 AM, Gary Lin wrote:
> > The x64 bpf jit expects bpf images converge within the given passes, but
> > it could fail to do so with some corner cases. For example:
> >
> >l0: ja 40
> >l1: ja 40
>
On 1/8/21 3:19 PM, Song Liu wrote:
To access per-task data, BPF program typically creates a hash table with
pid as the key. This is not ideal because:
1. The use need to estimate requires size of the hash table, with may be
inaccurate;
2. Big hash tables are slow;
3. To clean up the
Reviewed-by: Pavana Sharma
Reviewed-by: Pavana Sharma
On Sun, 2021-01-10 at 21:27 -0800, Jakub Kicinski wrote:
> Drop Felix from Mediatek Ethernet driver maintainers.
> We haven't seen any tags since the initial submission.
[]
> diff --git a/MAINTAINERS b/MAINTAINERS
[]
> @@ -11165,7 +11165,6 @@ F:Documentation/devicetree/bindings/dma/mtk-*
> F:
MT7530's LED controller can drive up to 15 LED/GPIOs.
Add support for GPIO control and allow users to use its GPIOs by
setting gpio-controller property in device tree.
Signed-off-by: DENG Qingfang
---
drivers/net/dsa/mt7530.c | 96
drivers/net/dsa/mt7530
Add device tree binding to support MT7530 GPIO controller.
Signed-off-by: DENG Qingfang
---
Documentation/devicetree/bindings/net/dsa/mt7530.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
b/Documentation/devicetree/bindings/net
MT7530's LED controller can be used as GPIO controller. Add support for
it.
DENG Qingfang (2):
dt-bindings: net: dsa: add MT7530 GPIO controller binding
drivers: net: dsa: mt7530: MT7530 optional GPIO support
.../devicetree/bindings/net/dsa/mt7530.txt| 6 ++
drivers/net/dsa/mt7530.c
On Sun, Jan 10, 2021 at 9:28 PM Jakub Kicinski wrote:
>
> Jay was not active in recent years and does not have plans
> to return to work on ATLX drivers.
>
> Subsystem ATLX ETHERNET DRIVERS
> Changes 20 / 116 (17%)
> Last activity: 2020-02-24
> Jay Cliburn :
> Chris Snook :
> Tags ea97
On Sun, Jan 10, 2021 at 10:23:06AM -0700, David Ahern wrote:
> On 1/2/21 11:17 PM, Leon Romanovsky wrote:
> > From: Patrisious Haddad
> >
> > Add support in rdma for extack errors to be received
> > in userspace when sent from kernel, so now netlink extack
> > error messages sent from kernel would
bareudp_dellink() only needs the device list to hand it to
unregister_netdevice_queue(). We can pass NULL in, and
unregister_netdevice_queue() will do the unregistering.
There is no chance for batching on the error path, anyway.
Suggested-by: Cong Wang
Signed-off-by: Jakub Kicinski
---
drivers/
Shrijeet has moved on from VRF-related work.
Subsystem VRF
Changes 30 / 120 (25%)
Last activity: 2020-12-09
David Ahern :
Author 1b6687e31a2d 2020-07-23 00:00:00 1
Tags 9125abe7b9cb 2020-12-09 00:00:00 4
Shrijeet Mukherjee :
Top reviewers:
[13]: dsah...@gmail.com
[4]: d..
Move Alexey to CREDITS.
I am probably not giving him enough justice with
the description line..
Subsystem NETWORKING [IPv4/IPv6]
Changes 1535 / 5111 (30%)
Last activity: 2020-12-10
"David S. Miller" :
Author b7e4ba9a91df 2020-12-09 00:00:00 407
Committer e0fecb289ad3 2020-12-10 00:0
We haven't heard from Mirko in 6 years.
There are only 57 changes to this driver, but it seems
like a pretty clear cut case.
Subsystem MARVELL GIGABIT ETHERNET DRIVERS (skge/sky2)
Changes 11 / 57 (19%)
Last activity: 2020-11-11
Mirko Lindner :
Stephen Hemminger :
Author 5aafeb74b5bb 2
Move Wensong Zhang to credits, we haven't heard from
him in years.
Subsystem IPVS
Changes 83 / 226 (36%)
Last activity: 2020-11-27
Wensong Zhang :
Simon Horman :
Committer c24b75e0f923 2019-10-24 00:00:00 33
Tags 7980d2eabde8 2020-10-12 00:00:00 76
Julian Anastasov :
Author 7
Drop Felix from Mediatek Ethernet driver maintainers.
We haven't seen any tags since the initial submission.
Not adding a CREDITS entry because summarizing Felix's
contributions as "initial Mediatek MT7623 driver" is
really selling it short. And Felix is not gone, so he
can write his own descripti
Hi!
This series intends to remove some most evidently inactive maintainers.
To make maintainers' lives easier we're trying to nudge people
towards CCing all the relevant folks on patches, in an attempt
to improve review rate. We have a check in patchwork which validates
the CC list against get_ma
As far as I can tell we haven't heard from Gerrit for roughly
5 years now. DCCP patch would really benefit from some review.
Gerrit was the last maintainer so mark this entry as orphaned.
Subsystem DCCP PROTOCOL
Changes 38 / 166 (22%)
(No activity)
Top reviewers:
[6]: kstew...@linuxfound
Aviad wrote parts of the initial TLS implementation
but hasn't been contributing to TLS since.
Subsystem NETWORKING [TLS]
Changes 123 / 308 (39%)
Last activity: 2020-12-01
Boris Pismenny :
Tags 138559b9f99d 2020-11-17 00:00:00 1
Aviad Yehezkel :
John Fastabend :
Author e91de6afa8
While ENA has 3 reviewers and 2 maintainers, we mostly see review
tags and comments from the maintainers. While we very much appreciate
Zorik's invovment in the community let's trim the reviewer list
down to folks we've seen tags from.
Subsystem AMAZON ETHERNET DRIVERS
Changes 13 / 269 (4%)
La
Jay was not active in recent years and does not have plans
to return to work on ATLX drivers.
Subsystem ATLX ETHERNET DRIVERS
Changes 20 / 116 (17%)
Last activity: 2020-02-24
Jay Cliburn :
Chris Snook :
Tags ea973742140b 2020-02-24 00:00:00 1
Top reviewers:
[4]: and...@lunn.ch
syzbot has bisected this issue to:
commit 4680a7ee5db27772af40d83393fa0fb955b745b7
Author: Miklos Szeredi
Date: Sat Oct 1 05:32:33 2016 +
fuse: remove duplicate cs->offset assignment
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=11fc80e750
start commit: 73b7a604 n
Some multigig SFPs from RollBall and Hilink do not expose functional
MDIO access to the internal PHY of the SFP via I2C address 0x56
(although there seems to be read-only clause 22 access on this address).
Instead these SFPs PHY can be accessed via I2C via the SFP Enhanced
Digital Diagnostic Inter
This adds support for multigig copper SFP modules from RollBall/Hilink.
These modules have a specific way to access clause 45 registers of the
internal PHY.
We also need to wait at least 22 seconds after deasserting TX disable
before accessing the PHY. The code waits for 25 seconds just to be sure
Instead of configuring the I2C mdiobus when SFP driver is probed,
create/destroy the mdiobus before the PHY is probed for/after it is
released.
This way we can tell the mdio-i2c code which protocol to use for each
SFP transceiver.
Signed-off-by: Marek Behún
Cc: Andrew Lunn
Cc: Russell King
---
Some SFPs may contain an internal PHY which may in some cases want to
connect with the host interface in 1000base-x/2500base-x mode.
Do not fail if such PHY is being attached in one of these PHY interface
modes.
Signed-off-by: Marek Behún
Reviewed-by: Russell King
Cc: Andrew Lunn
---
drivers/n
Hello,
this is v4 of series adding support for RollBall/Hilink SFP modules.
Checked with:
checkpatch.pl --max-line-length=80
Changes from v3:
- RollBall mdio-i2c driver now sets/restores SFP_PAGE for every MDIO
access.
I first wanted to achieve this operation (setting
SFP_PAGE/doing MDIO
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
Add per-CPU variable to bpf_testmod.ko and use those from new selftest to
validate it works end-to-end.
Signed-off-by: Andrii Nakryiko
Ack with a nit below.
Acked-by: Yonghong Song
---
.../selftests/bpf/bpf_testmod/bpf_testmod.c | 3 ++
.
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
Add support for searching for ksym externs not just in vmlinux BTF, but across
all module BTFs, similarly to how it's done for CO-RE relocations. Kernels
that expose module BTFs through sysfs are assumed to support new ldimm64
instruction extension wit
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
Add support for directly accessing kernel module variables from BPF programs
using special ldimm64 instructions. This functionality builds upon vmlinux
ksym support, but extends ldimm64 with src_reg=BPF_PSEUDO_BTF_ID to allow
specifying kernel module B
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
If some of the subtests use module BTFs through ksyms, they will cause
bpf_prog to take a refcount on bpf_testmod module, which will prevent it from
successfully unloading. Module's refcnt is decremented when bpf_prog is freed,
which generally happens
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
__bpf_free_used_maps() is always defined in kernel/bpf/core.c, while
include/linux/bpf.h is guarding it behind CONFIG_BPF_SYSCALL. Move it out of
that guard region and fix compiler warning.
Reported-by: kernel test robot
Fixes: a2ea07465c8d ("bpf: Fi
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
Add bpf_patch_call_args() prototype. This function is called from BPF verifier
and only if CONFIG_BPF_JIT_ALWAYS_ON is not defined. This fixes compiler
warning about missing prototype in some kernel configurations.
Reported-by: kernel test robot
Fixe
On 1/8/21 2:09 PM, Andrii Nakryiko wrote:
BPF interpreter uses extra input argument, so re-casts __bpf_call_base into
__bpf_call_base_args. Avoid compiler warning about incompatible function
prototypes by casting to void * first.
Reported-by: kernel test robot
Fixes: 1ea47e01ad6e ("bpf: add
Jakub Kicinski [k...@kernel.org] wrote:
> On Thu, 7 Jan 2021 23:12:34 -0800 Sukadev Bhattiprolu wrote:
> > Use a separate lock to serialze ibmvnic_reset() and ibmvnic_remove()
> > functions. ibmvnic_reset() schedules work for the worker thread and
> > ibmvnic_remove() flushes the work before remov
Jakub Kicinski [k...@kernel.org] wrote:
> On Thu, 7 Jan 2021 23:12:31 -0800 Sukadev Bhattiprolu wrote:
> > The reset functions need just the 'reset reason' parameter and not
> > the ibmvnic_rwi list element. Update the functions so we can simplify
> > the handling of the ->rwi_list in a follow-on
On 2021-01-08 22:35, Steffen Klassert wrote:
> On Fri, Jan 08, 2021 at 09:52:28PM +0900, Dongseok Yi wrote:
> > It is a workaround patch.
> >
> > UDP/IP header of UDP GROed frag_skbs are not updated even after NAT
> > forwarding. Only the header of head_skb from ip_finish_output_gso ->
> > skb_gso_
From: Pavana Sharma
Add 5gbase-r PHY interface mode.
Signed-off-by: Pavana Sharma
Reviewed-by: Andrew Lunn
Reviewed-by: Marek Behún
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/net/ethernet-controller.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devi
On Mon, Jan 11, 2021, at 04:31, Shay Agroskin wrote:
> Is this addition needed ? Seems like we don't set VIRTIO_XDP_TX
> bit in case of virtnet_xdp_xmit() failure, so the surrounding 'if'
> won't be taken.
Good catch, it looks like you're right. I'm happy to remove that extra branch
although I
From: Pavana Sharma
The Marvell 88E6393X device is a single-chip integration of a 11-port
Ethernet switch with eight integrated Gigabit Ethernet (GbE)
transceivers and three 10-Gigabit interfaces.
This patch adds functionalities specific to mv88e6393x family (88E6393X,
88E6193X and 88E6191X).
T
The 16-bit Port Policy CTL register from older chips is on 6393x changed
to Port Policy MGMT CTL, which can access more data, but indirectly and
via 8-bit registers.
The original 16-bit value is divided into first two 8-bit register in
the Port Policy MGMT CTL.
We can therefore use the previous c
From: Pavana Sharma
Returning 0 is no more an error case with MV88E6393 family
which has serdes lane numbers 0, 9 or 10.
So with this change .serdes_get_lane will return lane number
or -errno (-ENODEV or -EOPNOTSUPP).
Signed-off-by: Pavana Sharma
Reviewed-by: Andrew Lunn
Reviewed-by: Marek Beh
There are two implementations of the .set_egress_port method, and both
of them, if successful, set chip->*gress_dest_port variable.
To avoid code repetition, wrap this method into
mv88e6xxx_set_egress_port.
Signed-off-by: Marek Behún
---
drivers/net/dsa/mv88e6xxx/chip.c| 48
From: Pavana Sharma
Add 5GBASE-R phy interface mode
Signed-off-by: Pavana Sharma
Reviewed-by: Andrew Lunn
Reviewed-by: Marek Behún
---
include/linux/phy.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 9effb511acde..548372eb253a 100644
Hello,
so I took Pavana's patches for Amethyst and did some more work on this.
I am sending version 14, which should apply cleanly on net-next.
This series is tested on Marvell CN9130-CRB.
Changes from v13:
- added patch that wraps .set_egress_port into mv88e6xxx_set_egress_port,
so that we do
syzbot has found a reproducer for the following issue on:
HEAD commit:73b7a604 net: dsa: bcm_sf2: support BCM4908's integrated s..
git tree: net-next
console output: https://syzkaller.appspot.com/x/log.txt?x=12ec4a48d0
kernel config: https://syzkaller.appspot.com/x/.config?x=9ce3412
syzbot suspects this issue was fixed by commit:
commit 537cf4e3cc2f6cc9088dcd6162de573f603adc29
Author: Magnus Karlsson
Date: Fri Nov 20 11:53:39 2020 +
xsk: Fix umem cleanup bug at socket destruct
bisection log: https://syzkaller.appspot.com/x/bisect.txt?x=139f3dfb50
start commi
[ CC += netdev ]
On 1/10/21 5:38 PM, Pali Rohár wrote:
> On Saturday 02 January 2021 19:39:52 Pali Rohár wrote:
>> Also add description for struct in6_ifreq which is used for IPv6 addresses.
>>
>> SIOCSIFADDR and SIOCDIFADDR can be used to add or delete IPv6 address and
>> pppd is using these ioct
Clean up the remainings of rtl_pll_power_down/up and rename
rtl_pll_power_down() to rtl_prepare_power_down().
Signed-off-by: Heiner Kallweit
---
drivers/net/ethernet/realtek/r8169_main.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/realtek/
Realtek provided a description of bits 6 and 7 in register PMCH.
They configure whether the chip powers down certain PLL in D3hot and
D3cold respectively. They do not actually power down the PLL.
Reflect this in the code and configure D3 PLL powerdown based on
whether WOL is enabled.
Signed-off-by
There's no known reason why PLL powerdown on D3 shouldn't be enabled
on chip versions 34, 35, 36, and 42. At least the vendor driver doesn't
exclude any of these chip versions.
Signed-off-by: Heiner Kallweit
---
drivers/net/ethernet/realtek/r8169_main.c | 11 ---
1 file changed, 4 insert
On 1/8/21 11:44 AM, Andrii Nakryiko wrote:
Add comments clarifying that USER variants of CO-RE reading macro are still
only going to work with kernel types, defined in kernel or kernel module BTF.
This should help preventing invalid use of those macro to read user-defined
types (which doesn't
This series includes improvements to handling of PLL power-down.
Heiner Kallweit (3):
r8169: enable PLL power-down for chip versions 34, 35, 36, 42
r8169: improve handling D3 PLL power-down
r8169: clean up rtl_pll_power_down/up functions
drivers/net/ethernet/realtek/r8169_main.c | 65 +
From: Stefan Chulski
Packet Processor hardware not connected to MAC flow control unit and
cannot support TX flow control.
This patch disable flow control support.
Fixes: 3f518509dedc ("ethernet: Add new driver for Marvell Armada 375 network
unit")
Signed-off-by: Stefan Chulski
---
drivers/net
On Sun, Jan 10, 2021 at 07:11:53PM +, Stefan Chulski wrote:
> >
> > On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > > > not connected to the GOP flow control generation mechanism.
> > > > > To solve this issue Armada has firmware running on CM3 CPU
> > > > > dedectated fo
>
> On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > > not connected to the GOP flow control generation mechanism.
> > > > To solve this issue Armada has firmware running on CM3 CPU
> > > > dedectated for Flow Control support. Firmware monitors Packet
> > > > Processor resourc
On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > not connected to the GOP flow control generation mechanism.
> > > To solve this issue Armada has firmware running on CM3 CPU dedectated
> > > for Flow Control support. Firmware monitors Packet Processor resources
> > > and assert
On Sun, Jan 10, 2021 at 06:55:11PM +, Stefan Chulski wrote:
> > > not connected to the GOP flow control generation mechanism.
> > > To solve this issue Armada has firmware running on CM3 CPU dedectated
> > > for Flow Control support. Firmware monitors Packet Processor resources
> > > and assert
> > not connected to the GOP flow control generation mechanism.
> > To solve this issue Armada has firmware running on CM3 CPU dedectated
> > for Flow Control support. Firmware monitors Packet Processor resources
> > and asserts XON/XOFF by writing to Ports Control 0 Register.
>
> What is the mini
> Sorry, but that is not really a decision the driver can make. It is part of a
> kernel
> that _does_ support CPU hotplug, and the online CPUs can be changed today.
>
> It is likely that every distro out there builds the kernel with CPU hotplug
> enabled.
>
> If changing the online CPUs causes
On Sun, Jan 10, 2021 at 06:27:57PM +, Stefan Chulski wrote:
> > What also concerns me is whether flow control is supported in the existing
> > driver at all, given this patch set. If it isn't supported without the
> > firmware's
> > help, then we should _not_ be negotiating flow control with t
On Sun, Jan 10, 2021 at 06:24:30PM +, Stefan Chulski wrote:
> > >
> > > +/* Routine calculate single queue shares address space */ static int
> > > +mvpp22_calc_shared_addr_space(struct mvpp2_port *port) {
> > > + /* If number of CPU's greater than number of threads, return last
> > > + * addr
> > @@ -5373,6 +5402,30 @@ static int
> mvpp2_ethtool_set_pause_param(struct net_device *dev,
> > struct ethtool_pauseparam *pause) {
> > struct mvpp2_port *port = netdev_priv(dev);
> > + int i;
> > +
> > + if (pause->tx_pause && port->priv->global_tx_f
On Sun, Jan 10, 2021 at 06:09:39PM +, Stefan Chulski wrote:
> > > > > + } else {
> > > > > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
> > > > > + if (!priv->sram_pool) {
> > > > > + dev_warn(&pdev->dev, "DT is too old, TX FC
> > > > di
> >
> > +/* Routine calculate single queue shares address space */ static int
> > +mvpp22_calc_shared_addr_space(struct mvpp2_port *port) {
> > + /* If number of CPU's greater than number of threads, return last
> > +* address space
> > +*/
> > + if (num_active_cpus() >= MVPP2_MAX_THREA
Hi,
On Sun, Jan 10, 2021 at 05:30:04PM +0200, stef...@marvell.com wrote:
> Armada hardware has a pause generation mechanism in GOP (MAC).
> GOP has to generate flow control frames based on an indication
> programmed in Ports Control 0 Register. There is a bit per port.
> However assertion of the P
On Sun, Jan 10, 2021 at 05:30:18PM +0200, stef...@marvell.com wrote:
> @@ -5373,6 +5402,30 @@ static int mvpp2_ethtool_set_pause_param(struct
> net_device *dev,
>struct ethtool_pauseparam *pause)
> {
> struct mvpp2_port *port = netdev_priv(dev);
> +
> > > > + } else {
> > > > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
> > > > + if (!priv->sram_pool) {
> > > > + dev_warn(&pdev->dev, "DT is too old, TX FC
> > > disabled\n");
> > >
> > > I don't see anything in this patch that di
On Sun, Jan 10, 2021 at 05:30:16PM +0200, stef...@marvell.com wrote:
> + /* Enable global Flow Control only if hanler to SRAM not NULL */
I think this comment needs fixing. I'm not sure what a "hanler" is,
and "handler" doesn't make sense here.
--
RMK's Patch system: https://www.arml
On Sun, Jan 10, 2021 at 05:30:15PM +0200, stef...@marvell.com wrote:
> From: Stefan Chulski
>
> This patch did not change any functionality.
> Added flow control RXQ and BM pool config callbacks that would be
> used to configure RXQ and BM pool thresholds.
> APIs also will disable/enable RXQ and
On Sun, Jan 10, 2021 at 05:57:14PM +, Stefan Chulski wrote:
> > > + } else {
> > > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
> > > + if (!priv->sram_pool) {
> > > + dev_warn(&pdev->dev, "DT is too old, TX FC
> > disabled\n");
> >
> > I don't see any
> > + } else {
> > + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
> > + if (!priv->sram_pool) {
> > + dev_warn(&pdev->dev, "DT is too old, TX FC
> disabled\n");
>
> I don't see anything in this patch that disables TX flow control, which means
> this
On Sun, Jan 10, 2021 at 05:30:07PM +0200, stef...@marvell.com wrote:
> + } else {
> + priv->sram_pool = of_gen_pool_get(dn, "cm3-mem", 0);
> + if (!priv->sram_pool) {
> + dev_warn(&pdev->dev, "DT is too old, TX FC disabled\n");
I don't see anything i
> > @@ -5373,6 +5402,30 @@ static int
> mvpp2_ethtool_set_pause_param(struct net_device *dev,
> > struct ethtool_pauseparam *pause) {
> > struct mvpp2_port *port = netdev_priv(dev);
> > + int i;
> > +
> > + if (pause->tx_pause && port->priv->global_tx_f
>
> > > Should there be -EPROBE_DEFER handling in here somewhere? The SRAM
> > > is a device, so it might not of been probed yet?
> >
>
> > No, firmware probed during bootloader boot and we can use SRAM. SRAM
> > memory can be safely used.
>
> A previous patch added:
>
> + CP11X_L
> > Should there be -EPROBE_DEFER handling in here somewhere? The SRAM is a
> > device, so it might not of been probed yet?
>
> No, firmware probed during bootloader boot and we can use SRAM. SRAM
> memory can be safely used.
A previous patch added:
+ CP11X_LABEL(cm3_sram): cm3@22
On Sun, Jan 10, 2021 at 05:30:22PM +0200, stef...@marvell.com wrote:
> From: Stefan Chulski
>
> This patch add ring size validation before enabling FC.
> 1. Flow control cannot be enabled if ring size is below start
> threshold.
> 2. Flow control disabled if ring size set below start
> threshold.
> @@ -5373,6 +5402,30 @@ static int mvpp2_ethtool_set_pause_param(struct
> net_device *dev,
>struct ethtool_pauseparam *pause)
> {
> struct mvpp2_port *port = netdev_priv(dev);
> + int i;
> +
> + if (pause->tx_pause && port->priv->global_tx_fc
Charlie Somerville writes:
No send queues will be allocated for XDP filters. Attempts to
transmit
packets when no XDP send queues exist will fail with EOPNOTSUPP.
Signed-off-by: Charlie Somerville
---
drivers/net/virtio_net.c | 17 +
1 file changed, 13 insertions(+), 4 del
> External Email
>
> --
> On Sun, Jan 10, 2021 at 05:30:10PM +0200, stef...@marvell.com wrote:
> > From: Stefan Chulski
> >
> > BM pool size increased to support Firmware Flow Control.
> > Minimum depletion thresholds to support
On 1/2/21 11:17 PM, Leon Romanovsky wrote:
> From: Patrisious Haddad
>
> Add support in rdma for extack errors to be received
> in userspace when sent from kernel, so now netlink extack
> error messages sent from kernel would be printed for the
> user.
>
> Signed-off-by: Patrisious Haddad
> Sig
On 1/7/21 8:23 AM, Ido Schimmel wrote:
> From: Ido Schimmel
>
> Two small usage improvements in ip-nexthop and ip-monitor. Noticed while
> adding support for resilient nexthop groups.
>
> Ido Schimmel (2):
> nexthop: Fix usage output
> ipmonitor: Mention "nexthop" object in help and man page
On Sun, Jan 10, 2021 at 05:30:10PM +0200, stef...@marvell.com wrote:
> From: Stefan Chulski
>
> BM pool size increased to support Firmware Flow Control.
> Minimum depletion thresholds to support FC is 1024 buffers.
> BM pool size increased to 2048 to have some 1024 buffers
> space between depleti
> -Original Message-
> From: Andrew Lunn
> Sent: Sunday, January 10, 2021 7:05 PM
> To: Stefan Chulski
> Cc: netdev@vger.kernel.org; thomas.petazz...@bootlin.com;
> da...@davemloft.net; Nadav Haklai ; Yan Markman
> ; linux-ker...@vger.kernel.org; k...@kernel.org;
> li...@armlinux.org.u
> +static int mvpp2_get_sram(struct platform_device *pdev,
> + struct mvpp2 *priv)
> +{
> + struct device_node *dn = pdev->dev.of_node;
> + struct resource *res;
> +
> + if (has_acpi_companion(&pdev->dev)) {
> + res = platform_get_resource(pdev, IORESOU
On Sun, Jan 10, 2021 at 02:54:36PM +, Russell King wrote:
> Convert at803x_clk_out_config() to use phy_modify_mmd().
>
> Signed-off-by: Russell King
Reviewed-by: Andrew Lunn
Andrew
On Sun, Jan 10, 2021 at 10:58:37AM +, Russell King wrote:
> Extend the bitrate-derived support to include 2500BASE-X for modules
> that report a bitrate of 2500Mbaud.
>
> Signed-off-by: Russell King
Reviewed-by: Andrew Lunn
Andrew
On Sun, Jan 10, 2021 at 10:58:32AM +, Russell King wrote:
> The SFP MSA defines two option bits in byte 65 to indicate how the
> Rx_LOS signal on SFP pin 8 behaves:
>
> bit 2 - Loss of Signal implemented, signal inverted from standard
> definition in SFP MSA (often called "Signal Detec
On Sun, Jan 10, 2021 at 11:13:44AM +, Russell King wrote:
> Check whether the MAC driver has implemented the get_ts_info()
> method first, and call it if present. If this method returns
> -EOPNOTSUPP, defer to the phylib or default implementation.
>
> This allows network drivers such as mvpp2
On Sun, Jan 10, 2021 at 05:52:21PM +0900, Yuusuke Ashizuka wrote:
> RTL9000AA/AN as 100BASE-T1 is following:
> - 100 Mbps
> - Full duplex
> - Link Status Change Interrupt
Hi Yuusuke
For T1, it seems like Master is pretty important. Do you have
information to be able to return the current Master/s
From: Stefan Chulski
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 +-
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45
2 files cha
On 2021-01-10 04:19, Jakub Kicinski wrote:
On Wed, 6 Jan 2021 22:32:00 +0100 Rafał Miłecki wrote:
From: Rafał Miłecki
This helps validating DTS files. Only the current (not deprecated one)
binding was converted.
Minor changes:
1. Dropped dsa/dsa.txt references
2. Updated node name to match d
From: Stefan Chulski
Spinlock added to MSS shared memory configuration space.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 5 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 3 +++
2 files changed, 8 insertions(+)
diff --git a/drivers/net/etherne
From: Stefan Chulski
This patch add RXQ flow control configurations.
Patch do not enable flow control itself, flow control
disabled by default.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 +++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 7 +++
From: Stefan Chulski
This patch fix GMAC TX flow control autoneg.
Flow control autoneg wrongly were disabled with enabled TX
flow control.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
From: Stefan Chulski
This patch add ring size validation before enabling FC.
1. Flow control cannot be enabled if ring size is below start
threshold.
2. Flow control disabled if ring size set below start
threshold.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main
From: Stefan Chulski
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 39
2 files changed,
From: Stefan Chulski
New FIFO flow control feature were added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ&BM flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s
From: Stefan Chulski
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
Signed-o
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