On Tue, 26 Jul 2022 at 23:15, Jeff Tantsura wrote:
> In general, if we look at the whole spectrum, on one side there’re massively
> parallelized “many core” RTC ASICs, such as Trio, Lightspeed, and similar (as
> the last gasp of Redback/Ericsson venture - we have built 1400 HW threads
> ASIC (
On Tue, 26 Jul 2022 at 21:28, wrote:
> >No you are right, FP has much much more PPEs than Trio.
>
> Can you give any examples?
Nokia FP is like >1k, Juniper Trio is closer to 100 (earlier Trio LUs
had much less). I could give exact numbers for EA and YT if needed,
they are visible in the CLI and
As Lincoln said - all of us directly working with BCM/other silicon vendors
have signed numerous NDAs.
However if you ask a well crafted question - there’s always a way to talk about
it ;-)
In general, if we look at the whole spectrum, on one side there’re massively
parallelized “many core” RTC
mandatory slide of laundry analogy for pipelining
https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html
On Tue, 26 Jul 2022 at 12:41, Lawrence Wobker wrote:
>
>> "Pipeline" in the context of networking chips is not a terribly
>> well-defined term. In some ch
>
>
> "Pipeline" in the context of networking chips is not a terribly
> well-defined term. In some chips, you'll have a pipeline that is built
> from very rigid hardware logic blocks -- the first block does exactly one
> part of the packet forwarding, then hands the packet (or just the header
> an
On 25 July 2022 19:02:50 UTC, Saku Ytti wrote:
>On Mon, 25 Jul 2022 at 21:51, James Bensley wrote:
>
>> I have no frame of reference here, but in comparison to Gen 6 Trio of
>> NP5, that seems very high to me (to the point where I assume I am
>> wrong).
>
>No you are right, FP has much much more
I'll provide a bit more detail - We have certainly been
standardizing on 100G for a number of years now and have a decreasing
number of devices where 10G is appropriate.
for public peering we certainly do have an open peering policy,
if you are encountering an issue please reach ou
Akamai isn't supporting 10g ports on IXPs. I'd be surprised if the allowed
it on PNIs. As for not being on the IXPs, that's odd.
On Tue, Jul 26, 2022 at 8:23 AM Jawaid Bazyar
wrote:
> Hi,
>
>
>
> We had Akamai servers in our data center for many years until a couple
> years ago, when they said
Hi,
We had Akamai servers in our data center for many years until a couple years
ago, when they said they’d changed their policies and decommissioned the
servers.
I understand that, maintaining many server sites and being responsible for that
hardware, even if you pay nothing for power or coll
Pipeline Stages are like separate computers (with their own ALU) sharing the
same memory.
In the ASIC case, the computers have different types (different capabilities).
From: Etienne-Victor Depasquale [mailto:ed...@ieee.org]
Sent: Tuesday, July 26, 2022 2:05 PM
To: Saku Ytti
Cc: Vasilenko Eduard
>
> How do you define a pipeline?
For what it's worth, and
with just a cursory look through this email, and
without wishing to offend anyone's knowledge:
a pipeline in processing is the division of the instruction cycle into a
number of stages.
General purpose RISC processors are often organized
Nope, ASIC vendors are not ARM-based for PFE. Every “stage” is a very
specialized ASIC with small programmability (not so small for P4 and some
latest generation ASICs).
ARM cores are for Network Processors (NP). ARM cores (with proper microcode)
could emulate any “stage” of ASIC. It is the typi
On Tue, 26 Jul 2022 at 10:52, Vasilenko Eduard
wrote:
> Juniper is pipeline-based too (like any ASIC). They just invented one
> special stage in 1996 for lookup (sequence search by nibble in the big
> external memory tree) – it was public information up to 2000year. It is a
> different principle
All high-performance networking devices on the market have pipeline
architecture.
The pipeline consists of "stages".
ASICs have stages fixed to particular functions:
[cid:image002.png@01D8A0DD.988EC6A0]
Well, some stages are driven by code our days (a little flexibility).
Juniper is pipel
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