On Tue, 26 Jul 2022 at 23:15, Jeff Tantsura <jefftant.i...@gmail.com> wrote:
> In general, if we look at the whole spectrum, on one side there’re massively > parallelized “many core” RTC ASICs, such as Trio, Lightspeed, and similar (as > the last gasp of Redback/Ericsson venture - we have built 1400 HW threads > ASIC (Spider). > On another side of the spectrum - fixed pipeline ASICs, from BCM Tomahawk at > its extreme (max speed/radix - min features) moving with BCM Trident, > Innovium, Barefoot(quite different animal wrt programmability), etc - usually > shallow on chip buffer only (100-200M). > > In between we have got so called programmable pipeline silicon, BCM DNX and > Juniper Express are in this category, usually a combo of OCB + off chip > memory (most often HBM), (2-6G), usually have line-rate/high scale > security/overlay encap/decap capabilities. Usually have highly optimized RTC > blocks within a pipeline (RTC within macro). The way and speed to access DBs, > memories is evolving with each generation, number/speed of non networking > cores(usually ARM) keeps growing - OAM, INT, local optimizations are primary > users of it. What do we call Nokia FP? Where you have a pipeline of identical cores doing different things, and the packet has to hit each core in line in order? How do we contrast this to NPU where a given packet hits exactly one core? I think ASIC, NPU, pipeline, RTC are all quite ambiguous. When we say pipeline, usually people assume a purpose build unique HW blocks packet travels through (like DNX, Express) and not fully flexible identical cores pipeline like FP. So I guess I would consider 'true pipeline', pipeline of unique HW blocks and 'true NPU' where a given packet hits exactly 1 core. And anything else as more or less hybrid. I expect once you get to the details of implementation all of these generalisations use communicative power. -- ++ytti
