Module submission Verilog::Preproc

The following module was proposed for inclusion in the Module List: modid: Verilog::Preproc DSLIP: Rd+Op description: Verilog language preprocessing userid: WSNYDER (Wilson Snyder) chapterid:9 (Language_Interfaces) communities: similar: rationale: It's

Module submission Verilog::Preproc

The following module was proposed for inclusion in the Module List: modid: Verilog::Preproc DSLIP: Rd+Op description: Language preprocessing, returning getline()s userid: WSNYDER (Wilson Snyder) chapterid:9 (Language_Interfaces) communities: similar: ration