The following module was proposed for inclusion in the Module List:

  modid:       Verilog::Preproc
  DSLIP:       Rd+Op
  description: Verilog language preprocessing
  userid:      WSNYDER (Wilson Snyder)
  chapterid:    9 (Language_Interfaces)
  communities:

  similar:

  rationale:

    It's used by Verilog::Netlist, and is also usable as a stand-alone
    preprocessor or by perl applications just like a IO::File handle
    would be used.

    Already used by dozens of users.

  enteredby:   WSNYDER (Wilson Snyder)
  enteredon:   Mon Apr  8 14:02:08 2002 GMT

The resulting entry would be:

Verilog::
::Preproc         Rd+Op Verilog language preprocessing               WSNYDER


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