Re: [Mesa-dev] [rong.r.y...@intel.com: [Intel-gfx] How user space applications load registers on HSW?]

think the command parser could be ready? Thanks Zou Nanhai -Original Message- From: daniel.vet...@ffwll.ch [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter Sent: Tuesday, May 13, 2014 2:11 PM To: Yang, Rong R Cc: Kenneth Graunke; Zou, Nanhai; mesa-dev; Ben Widawsky; intel-gfx

Re: [Mesa-dev] [PATCH 0/10] i965: Implement hiz and separate stencil for window framebuffer

Hi Chad, Glad to see the Hiz patches. Have you performance data for the Hiz patches, how much can this improve? Thanks Zou Nanhai -Original Message- From: mesa-dev-bounces+nanhai.zou=intel@lists.freedesktop.org [mailto:mesa-dev-bounces+nanhai.zou=intel

Re: [Mesa-dev] [PATCH 0/5] i965: die structs die!

Hi, What is the intention of switching struct-style command to OUT_BATCH style? Thanks Zou Nanhai >>-Original Message- >>From: mesa-dev-bounces+nanhai.zou=intel@lists.freedesktop.org >>[mailto:mesa-dev-bounces+nanhai.zou=intel@lists.freedesktop.o

Re: [Mesa-dev] [PATCH] i965: fix timer query on gen6+

>>-Original Message- >>From: Eric Anholt [mailto:e...@anholt.net] >>Sent: 2011年7月17日 8:08 >>To: Zou, Nanhai; mesa-dev@lists.freedesktop.org >>Subject: Re: [Mesa-dev] [PATCH] i965: fix timer query on gen6+ >> >>On Fri, 15 Jul 2011 18:07:51

Re: [Mesa-dev] [PATCH] i965: fix timer query on gen6+

For ILK, It is vol 1.18.11.2, This register has the contents from TIMESTAMP_HI (0x70070) display register. This field gets incremented every 1 uS of time. Thanks Zou Nanhai -Original Message- From: mesa-dev-bounces+nanhai.zou=intel

Re: [Mesa-dev] Mesa (master): i965: SNB GT1 has only 32k urb and max 128 urb entries.

>>-Original Message- >>From: Ian Romanick [mailto:i...@freedesktop.org] >>Sent: 2011年4月6日 11:06 >>To: mesa-dev@lists.freedesktop.org >>Cc: Zou, Nanhai >>Subject: Re: Mesa (master): i965: SNB GT1 has only 32k urb and max 128 urb >>entries. >

Re: [Mesa-dev] Mesa (master): i965: clear global offset to zero in m0.2 for VS DP read.

In fact this is not zero at multi vs thread cases on GT1, it will trigger DP read error when multi vs thread is enabled. I can not find where in spec says this payload M0.2 is reserved as zero, Thanks Zou Nan hai >>-Original Message- >>From: mesa-dev-bounces+nanhai.zou=intel@lists.f

Re: [Mesa-dev] Mesa (master): i965: clear global offset to zero in m0.2 for VS DP read.

>>-Original Message- >>From: Eric Anholt [mailto:e...@anholt.net] >>Sent: 2011年4月11日 23:32 >>To: Zou, Nanhai; mesa-dev@lists.freedesktop.org; >>mesa-com...@lists.freedesktop.org >>Subject: RE: [Mesa-dev] Mesa (master): i965: clear global offset to ze

Re: [Mesa-dev] Mesa (master): i965: clear global offset to zero in m0.2 for VS DP read.

That is a duplicated fix as commit 9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e. I have reverted the patch. Please pick 9d60a7ce08a67eb8b79c60f829d090ba4a37ed7e. Thanks Zou Nanhai >>-Original Message- >>From: Ian Romanick [mailto:i...@freedesktop.org] >>Sent: 2011年4月12日 0:20

Re: [Mesa-dev] [PATCH 2/2] i965: Quit spamming gen6 DP read/write send instructions with gen5 bits.

Eric, I think for gen6 most of the DP read in the pipeline should go through constant cache instead of other caches. Maybe we should implement an gen6_const_read_message. That is better for performance. Thanks Zou Nanhai >>-Original Message- >>From: mesa

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add gen6 register spilling support.

Hi Eric, BSpec says VS and WM should fall to single thread to avoid racing if use scratch space. Thanks Zou Nanhai >>-Original Message- >>From: mesa-dev-bounces+nanhai.zou=intel@lists.freedesktop.org >>[mailto:mesa-dev-bounces+nanhai.zou=intel@lists.f

Re: [Mesa-dev] [PATCH 1/2] i965/fs: Add gen6 register spilling support.

I think that probably not single thread. But Bspec says to recalculate max vs and wm thread if using scratch to avoid use out scrach space and to avoid deadlock. I don't know what the deadlock means there. Thanks Zou Nanhai >>-Original Message- >>From: mesa-dev-b