>>-----Original Message----- >>From: Eric Anholt [mailto:e...@anholt.net] >>Sent: 2011年4月11日 23:32 >>To: Zou, Nanhai; mesa-dev@lists.freedesktop.org; >>mesa-com...@lists.freedesktop.org >>Subject: RE: [Mesa-dev] Mesa (master): i965: clear global offset to zero in >>m0.2 for VS DP read. >> >>On Mon, 11 Apr 2011 17:16:34 +0800, "Zou, Nanhai" <nanhai....@intel.com> >>wrote: >>> In fact this is not zero at multi vs thread cases on GT1, it will trigger >>DP read error when multi vs thread is enabled. >>> >>> I can not find where in spec says this payload M0.2 is reserved as zero, >> >>g0.2 is delivered as 0. See vol2a.03: Thread Payload. We rely on that >>all over the place, not just in the VS. >> >>In brw_dp_read_4_vs, before your change, m0.2 was already getting set. >> >>In brw_dp_read_4_vs_relative, before your change, m0 was loaded with g0 >>through gen6_resolve_implied_move(p, &src, 0). >> >>In both cases, your change is dead instructions as far as I can see.
Oops, my mistake. I was fixing this bug https://bugs.freedesktop.org/show_bug.cgi?id=35730 on 7.10 branch. On that branch M0.2 was a random value with no gen6_resolve_implied_move. I made the patch then applied it to master, not noticed it was already fixed in master. Thanks Zou Nan hai _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
