[Mesa-dev] [PATCH 06/14] i965/blorp: Add support for loading vertices for glsl-based blits

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 5 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 94 2 files changed, 99 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h

[Mesa-dev] [PATCH 08/14] i965/blorp: Add support for setting samplers for glsl-based blits

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 2 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++ 2 files changed, 32 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h index

[Mesa-dev] [PATCH 04/14] i965/meta: Add helper for looking up blit programs

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_util.c | 148 ++ src/mesa/drivers/dri/i965/brw_meta_util.h | 9 ++ 2 files changed, 157 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 05/14] i965/blorp: Add plumbing for glsl-based color blits

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 27 + src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 90 2 files changed, 117 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 03/14] meta: Provide read access to blit shaders

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/common/meta.c | 17 - src/mesa/drivers/common/meta.h | 5 - 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index cf99d95..8c69b5d 100644

[Mesa-dev] [PATCH 02/14] i965/blorp/gen6: Support for loading glsl-based fragment shaders

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 1 + src/mesa/drivers/dri/i965/gen6_blorp.cpp | 74 2 files changed, 75 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h b/src/mesa/drivers/dri/i965/brw_blorp.h

[Mesa-dev] [PATCH 10/14] i965/blorp: Enable glsl-based fbo blits

20.87 12011.815 762.67232 + 137 13963.49 18281.85 17031.56 16985.443 712.08714 Difference at 95.0% confidence 4973.63 +/- 174.726 41.4061% +/- 1.45462% No visible changes in public benchmarks. No piglit regressions. Signed-off-by: Topi Pohjolainen --- src/mesa/driver

[Mesa-dev] [PATCH 09/14] i965/gen6: Add support for setting minimum layer for tex surfaces

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ad5ddb5..c006762 100644 --- a

[Mesa-dev] [PATCH 13/14] i965/blorp/gen6: Prepare vertex buffer setup logic for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++ 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index f45dcd4..22ea86c 100644

[Mesa-dev] [PATCH] Revert "i965: Restore vbo after color resolve during brw_try_draw_prims()"

lla: https://bugs.freedesktop.org/show_bug.cgi?id=94150 Signed-off-by: Topi Pohjolainen CC: Ben Widawsky CC: Ian Romanick Reviewed-by: Tapani Palli --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 9 - 1 file changed, 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_meta_fa

[Mesa-dev] [PATCH 03/14] i965: Expose draw primitive formatting

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c | 82 ++-- src/mesa/drivers/dri/i965/brw_draw.h | 7 +++ 2 files changed, 58 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 04/14] i965/blorp: Use meta utility for primitive emission

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 +++ src/mesa/drivers/dri/i965/brw_meta_util.c | 17 + src/mesa/drivers/dri/i965/brw_meta_util.h | 4 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 18 -- src/mesa/drivers/dri

[Mesa-dev] [PATCH 02/14] i965: Reduce scope of vertex access type

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index 323253e..c8a083c 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 01/14] i965: Reduce scope of indirect draw flag

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index c295d91..323253e 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 10/14] i965: Add means to override individual pipeline parts

This will allow meta programming to provide gl-state agnostic emitters. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h| 7 +++ src/mesa/drivers/dri/i965/brw_state_upload.c | 29 2 files changed, 28 insertions(+), 8 deletions

[Mesa-dev] [PATCH 06/14] i965/blorp: Move vertex buffer setup to meta util

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_util.c | 32 + src/mesa/drivers/dri/i965/brw_meta_util.h | 5 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 39 --- 3 files changed, 41 insertions(+), 35 deletions

[Mesa-dev] i965/meta: Bypass core vertex buffer setup

y CC: Ian Romanick Topi Pohjolainen (14): i965: Reduce scope of indirect draw flag i965: Reduce scope of vertex access type i965: Expose draw primitive formatting i965/blorp: Use meta utility for primitive emission i965/blorp: Refactor batch buffer save/restore i965/blorp: Move ver

[Mesa-dev] [PATCH 08/14] i965/meta: Prepare vertex buffer setup for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_util.c | 30 ++ 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c b/src/mesa/drivers/dri/i965/brw_meta_util.c index 8b9d5df..90cb1ce 100644

[Mesa-dev] [PATCH 11/14] i965: Introduce enumeration for atoms

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_atoms.h| 265 + src/mesa/drivers/dri/i965/brw_state_upload.c | 556 ++- 2 files changed, 556 insertions(+), 265 deletions(-) create mode 100644 src/mesa/drivers/dri/i965/brw_atoms.h

[Mesa-dev] [PATCH 13/14] i965/meta: Setup vertices for fast clear without core vbo support

Meta operations will setup vertices directly instead of interfering with core content vertex buffer object state. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181 Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.c | 2 + src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 07/14] i965/blorp: Move clipper disabling to meta util

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 3 --- src/mesa/drivers/dri/i965/brw_meta_util.c | 23 +++ src/mesa/drivers/dri/i965/brw_meta_util.h | 2 ++ src/mesa/drivers/dri/i965/gen6_blorp.cpp | 28 +--- src/mesa

[Mesa-dev] [PATCH 09/14] i965/gen8: Expose emission for system generated values

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.h | 6 ++ src/mesa/drivers/dri/i965/gen8_draw_upload.c | 101 +++ 2 files changed, 63 insertions(+), 44 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.h b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 05/14] i965/blorp: Refactor batch buffer save/restore

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 41 ++--- src/mesa/drivers/dri/i965/brw_context.h | 10 +++ src/mesa/drivers/dri/i965/brw_meta_util.c | 50 +++ src/mesa/drivers/dri/i965/brw_meta_util.h | 6

[Mesa-dev] [PATCH 12/14] i965/meta: Introduce custom pipeline

Meta gives core state upload a set of emit overrides programming vertex fetcher without core vbo support. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 3 + src/mesa/drivers/dri/i965/brw_meta_util.c | 216 ++ src/mesa/drivers/dri

[Mesa-dev] [PATCH 14/14] i965: Don't add fast cleared buffers to render cache

Color buffers are not really written and therefore there is no reason to flush the caches. (Render cache is a set of buffer object pointers controlling brw_render_cache_set_check_flush()). Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 +++-- 1 file

[Mesa-dev] [v3] Compression support for single-sampled

This revision changes the way buffer state is tracked. Instead of setting the state in surface-state setup, the state is now set as part of brw_postdraw_set_buffers_need_resolve(). And separately for rep-cleared buffers in set_render_buffers_state(). Topi Pohjolainen (5): i965/gen9: Prepare

[Mesa-dev] [v3 1/5] i965/gen9: Prepare surface state setup for lossless compression

brw_postdraw_set_buffers_need_resolve() using a separate patch. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_defines.h| 1 + src/mesa/drivers/dri/i965/gen8_surface_state.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa

[Mesa-dev] [v3 4/5] i965: Add helper for lossless compression support

v2: Check explicitly against base type of GL_FLOAT instead of using _mesa_is_format_integer_color(). Otherwise we miss GL_UNSIGNED_NORMALIZED. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 22 ++ src/mesa/drivers/dri/i965

[Mesa-dev] [v3 2/5] i965/gen8: Set render state for lossless compressed

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c| 7 ++- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 - 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c

[Mesa-dev] [v3 5/5] i965/gen9: Enable lossless compression

ation driver changing: Manhattan: 8.32152% +/- 0.355881% Offscreen: 9.09713% +/- 0.340763% Glb trex: 8.46231% +/- 0.460624% Offscreen: 9.31872% +/- 0.463743% v2 (Ben): Re-use msaa layout type for single sampled case. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_st

[Mesa-dev] [v3 3/5] i965/gen9: Setup MCS for compressed texture surfaces

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_surface_state.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index 8631c90..e696cac 100644 --- a/src

[Mesa-dev] [PATCH] i965/nir: Use uniform index instead of lookup by name

uniform linking does. Unfortunately I didn't see any improvement in performance tests, at least on BDW. Only the the fps numbers in a few synthetic benchmarks started to vary more than before between two subsequent runs. CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/driver

[Mesa-dev] [RFC] i965/dbg: Expose cases hitting a presumably dead optimization

e compiler just as param[]. (Filling pull_param is based on the pull locations and doesn't need to be inside the compiler). Any thoughts? Signed-off-by: Topi Pohjolainen CC: Ian Romanick CC: Kenneth Graunke CC: Eric Anholt --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 2 ++ 1 file change

[Mesa-dev] [PATCH 04/14] i965/blorp: Use prog data counters to guide sf/sbe setup

just as core upload logic does. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 3 ++- src/mesa/drivers/dri/i965/brw_blorp.h | 8 +++- src/mesa/drivers/dri/i965/gen6_blorp.c | 10 -- src/mesa/drivers/dri/i965/gen7_blorp.c | 10 -- src/mesa

[Mesa-dev] [PATCH 05/14] i965/blorp: Use prog data counters to guide wm/ps setup

just as core upload logic does. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 4 +++- src/mesa/drivers/dri/i965/gen7_blorp.c | 2 ++ src/mesa/drivers/dri/i965/gen8_blorp.c | 5 +++-- 3 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers

[Mesa-dev] [PATCH 13/14] i965: Do not flush texture and data port caches for clears

Clears don't sample or blend colors and therefore this is unnecessary. This was a difference between blorp and meta clears. This also drops the flushes for gen6_blorp_hiz_exec() which is used for depth clears and resolves. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri

[Mesa-dev] [PATCH 07/14] i965/urb: Allow blorp to record current settings

This makes it possible to skip urb re-configuration if the subsequent renders agree with the settings. Also allows blorp to allocate the maximun amount of vs entries available. Core upload logic already knows how to calculate this. Helps one synthetic benchmark. Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 08/14] i965/blorp: Fix the size requirement for vertex elements

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/gen7_blorp.c | 38 ++ src/mesa/drivers/dri/i965/gen8_blorp.c | 2 +- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers

[Mesa-dev] [PATCH 09/14] i965/fs: Provide compiler options using a flags argument

Signed-off-by: Topi Pohjolainen --- src/intel/vulkan/anv_pipeline.c | 6 -- src/mesa/drivers/dri/i965/brw_blorp.c | 5 ++--- src/mesa/drivers/dri/i965/brw_blorp.h | 3 +-- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 2 +- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 10/14] i965/fs: Add support for repclear without color setup

Fast color clears and resolves ignore the payload. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_compiler.h | 1 + src/mesa/drivers/dri/i965/brw_fs.cpp | 11 ++- src/mesa/drivers/dri/i965/brw_fs.h | 2 +- 3 files changed, 8 insertions(+), 6 deletions

[Mesa-dev] [PATCH 03/14] i965/blorp: Use core vertex buffer state setup

Also split the setup from the setup of vertex elements. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 102 - 1 file changed, 36 insertions(+), 66 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers

[Mesa-dev] [PATCH 11/14] i965/blorp: Ignore color setup in fast clears and resolves

W g114<8,8,1>F render RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT }; END B0 Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 43 --- 1 file changed, 33 insertions(+), 10 deletions(-) di

[Mesa-dev] [PATCH 01/14] i965/draw: Expose vertex buffer state setup

Also change the interface to use start and end offsets. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.h| 13 + src/mesa/drivers/dri/i965/brw_draw_upload.c | 42 - 2 files changed, 37 insertions(+), 18 deletions(-) diff --git

[Mesa-dev] [PATCH 12/14] i965/blorp/gen7+: Skip disabling already disabled stages

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.c | 16 src/mesa/drivers/dri/i965/gen8_blorp.c | 12 2 files changed, 28 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c index

[Mesa-dev] [PATCH 02/14] i965/gen8: Fix the vertex buffer size

And refactor to use the same upload logic with earlier gens. On gen >= 8 one doesn't provide ending address but number of bytes available. This is relative to the given offset. Until now we programmed the full size of the buffer regardless of the used offset. Signed-off-by: Topi Poh

[Mesa-dev] [PATCH 14/14] i965/blorp: Disable vertex element swizzling

Without vertex elements originating directly from vertex fetcher are not passed to wm-state correctly. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.c | 11 +-- src/mesa/drivers/dri/i965/gen8_blorp.c | 11 +-- 2 files changed, 18 insertions(+), 4

[Mesa-dev] [PATCH 06/14] i965/blorp: Let program data tell if push constants are needed

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 8 ++-- src/mesa/drivers/dri/i965/gen7_blorp.c | 16 +++- src/mesa/drivers/dri/i965/gen8_blorp.c | 26 ++ 3 files changed, 35 insertions(+), 15 deletions(-) diff --git a/src

[Mesa-dev] i965/blorp: Preparing for flat inputs + small optimizations

really prepares for flat inputs but might save us a few electrons even with current setup. Topi Pohjolainen (14): i965/draw: Expose vertex buffer state setup i965/gen8: Fix the vertex buffer size i965/blorp: Use core vertex buffer state setup i965/blorp: Use prog data counters to guide sf

[Mesa-dev] [PATCH 2/2] i965: Add norbc debug option

This INTEL_DEBUG option disables lossless compression (also known as render buffer compression). Suggested-by: Eero Tamminen Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_debug.c | 1 + src/mesa/drivers/dri/i965/intel_debug.h | 1 + src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 1/2] i965/gen9: Configure rbc buffers as plain for non-rbc tex views

much garbage. Fortunately none of tracked benchmarks showed a regression with this. Signed-off-by: Topi Pohjolainen CC: Kenneth Graunke DefaultGeometry.NumSamples); } +/* On Gen9 color buffers may be compressed by the hardware (lossless + * compression). There are, however, format

[Mesa-dev] [PATCH 04/18] i965/blorp: Use core vertex buffer state setup

Also split the setup from the setup of vertex elements. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 62 -- 1 file changed, 14 insertions(+), 48 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers

[Mesa-dev] i965/blorp: Use flat vertex inputs instead of uniforms

. Having them in vec4s drops the need to repack them. Last four patches take actual advantage of the change by dropping unnecessary pipeline reconfiguration. CC: Kenneth Graunke CC: Jason Ekstrand Topi Pohjolainen (18): i965/draw: Expose vertex buffer state setup i965: Unify vertex buffer setup

[Mesa-dev] [PATCH 01/18] i965/draw: Expose vertex buffer state setup

Also change the interface to use start and end offsets. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.h| 13 + src/mesa/drivers/dri/i965/brw_draw_upload.c | 42 - 2 files changed, 37 insertions(+), 18 deletions(-) diff --git

[Mesa-dev] [PATCH 03/18] i965/blorp: Split vertex data and element setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 46 ++ 1 file changed, 25 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index 7871a01..e9340df 100644 --- a

[Mesa-dev] [PATCH 02/18] i965: Unify vertex buffer setup

On gen >= 8 one doesn't provide ending address but number of bytes available. This is relative to the given offset. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 34 +++ src/mesa/drivers/dri/i965/gen8_draw_uploa

[Mesa-dev] [PATCH 09/18] i965/blorp: Store input read mask

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 1 + src/mesa/drivers/dri/i965/brw_blorp.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index ce37838..4d6c0ba 100644 --- a/src/mesa

[Mesa-dev] [PATCH 05/18] i965/blorp: Rename push constants to inputs

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 8 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 24 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 4 ++-- src/mesa/drivers/dri/i965/gen6_blorp.c| 6 +++--- src

[Mesa-dev] [PATCH 06/18] i965/blorp: Share input slot between pixel kill and blend/scaled

These are never used in parallel, lets document this. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 47 --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 82 ++- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 6 +- 3

[Mesa-dev] [PATCH 08/18] i965/blorp: Drop LOAD_UNIFORM macro

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 11 +++ 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index e021d23..1683f8e 100644 --- a/src

[Mesa-dev] [PATCH 07/18] i965/blorp: Load tranformation coordinates as vec4

In preparation for loading as flat vertex input. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 25 + 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 11/18] i965/blorp: Tell vertex fetcher about flat inputs

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 30 -- src/mesa/drivers/dri/i965/gen8_blorp.c | 8 ++-- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri

[Mesa-dev] [PATCH 14/18] i965/blorp: Remove support for push constants

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 17 ++- src/mesa/drivers/dri/i965/brw_blorp.h | 15 - src/mesa/drivers/dri/i965/gen6_blorp.c | 56 +- src/mesa/drivers/dri/i965/gen7_blorp.c | 41

[Mesa-dev] [PATCH 18/18] i965/blorp/gen7+: Do not trigger push constant space reconfig

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_urb.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 84648d1..24b45f1 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c

[Mesa-dev] [PATCH 16/18] i965/blorp: Fix the size requirement for vertex elements

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 3 ++- src/mesa/drivers/dri/i965/gen7_blorp.c | 38 ++ src/mesa/drivers/dri/i965/gen8_blorp.c | 2 +- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers

[Mesa-dev] [PATCH 15/18] i965/urb: Allow blorp to record current settings

This makes it possible to skip urb re-configuration if the subsequent renders agree with the settings. Also allows blorp to allocate the maximun amount of vs entries available. Core upload logic already knows how to calculate this. Helps one synthetic benchmark. Signed-off-by: Topi Pohjolainen

[Mesa-dev] [PATCH 10/18] i965/blorp: Add support for flat input buffer

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 68 -- 1 file changed, 65 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.c b/src/mesa/drivers/dri/i965/gen6_blorp.c index cd02b24..831ff3a 100644 --- a

[Mesa-dev] [PATCH 13/18] i965/blorp: Use flat inputs instead of uniforms

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 43 ++- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 9 +++--- 2 files changed, 27 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa

[Mesa-dev] [PATCH 17/18] i965/blorp/gen7+: Stop trashing push constant allocation

only needed for the 3DSTATE_CONSTANT_XS to be effective: From the BSpec: "The 3DSTATE_CONSTANT_* command is not committed to the shader unit until the corresponding (same shader) 3DSTATE_BINDING_TABLE_POINTER_* command is parsed." Signed-off-by: Topi Pohjolainen --- src/mesa

[Mesa-dev] [PATCH 12/18] i965/blorp: Prepare for more than two vertex attributes

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 13 + src/mesa/drivers/dri/i965/gen6_blorp.c | 4 +++- src/mesa/drivers/dri/i965/gen7_blorp.c | 4 +++- src/mesa/drivers/dri/i965/gen8_blorp.c | 4 +++- 4 files changed, 22 insertions(+), 3 deletions

[Mesa-dev] [PATCH] i965/gen8: Allow 16k viewport when blitting stencil

From: Topi Pohjolainen Fixes gles3 conformance tests: framebuffer_blit_functionality_negative_height_blit framebuffer_blit_functionality_negative_width_blit framebuffer_blit_functionality_negative_dimensions_blit framebuffer_blit_functionality_magnifying_blit

[Mesa-dev] i965/gen4: Depth buffer setup cleanup

offset zero. This gets fixed by patch 5. I considered fixing this first and only then do the cleanups but unfortunately that would make ugly even uglier. Topi Pohjolainen (6): i965/gen4: Remove non-existing stencil and hiz buffer setup i965/gen4: Remove redundant check for depth when rebas

[Mesa-dev] [PATCH 4/6] i965: Drop depth/stencil miptree pointers in alignment workaround

In brw_workaround_depthstencil_alignment() corresponding renderbuffers are always set to refer to the same temp miptrees. There is no need to carry them in context. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h| 3 --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 6/6] i965/gen4: Tell briefly how workaround depth gets reconciled

CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 85050ce..fe021b0 100644 --- a/src/mesa

[Mesa-dev] [PATCH 1/6] i965/gen4: Remove non-existing stencil and hiz buffer setup

Separate stencil and hiz are only enabled for gen6+. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h| 6 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 119 +++-- 2 files changed, 13 insertions(+), 112 deletions(-) diff --git a/src

[Mesa-dev] [PATCH 3/6] i965/gen4: Simplify depth/stencil invalidate check

There is no separate stencil on gen < 6. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_stat

[Mesa-dev] [PATCH 2/6] i965/gen4: Remove redundant check for depth when rebasing stencil

ere depth would refer to different surface than stencil. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 63 ++ 1 file changed, 11 insertions(+), 52 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/driv

[Mesa-dev] [PATCH 5/6] i965/gen4: Refactor depth/stencil rebase

-miplevels 1024 s=z24_s8 g45,ilk:depthstencil-render-miplevels 273 s=z24_s8 Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 232 - 1 file changed, 63 insertions(+), 169 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 6/7] i965/gen4: Refactor depth/stencil rebase

Effectively there is the same code twice, once for depth and again for stencil. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 243 - 1 file changed, 63 insertions(+), 180 deletions(-) diff --git a/src/mesa/drivers/dri/i965

[Mesa-dev] [v2 2/7] i965/gen4: Remove non-existing stencil and hiz buffer setup

Separate stencil and hiz are only enabled for gen6+. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h| 6 +- src/mesa/drivers/dri/i965/brw_misc_state.c | 120 +++-- 2 files changed, 14 insertions(+), 112 deletions(-) diff --git a/src

[Mesa-dev] [v2 1/7] i965/gen4: Set depth offset when there is stencil attachment only

...@lists.freedesktop.org Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index afa7e08..66f8555 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [v2 7/7] i965/gen4: Tell briefly how workaround depth gets reconciled

CC: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 85050ce..fe021b0 100644 --- a/src/mesa

[Mesa-dev] [v2 3/7] i965/gen4: Remove redundant check for depth when rebasing stencil

ere depth would refer to different surface than stencil. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 63 ++ 1 file changed, 12 insertions(+), 51 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/driv

[Mesa-dev] [v2 4/7] i965/gen4: Simplify depth/stencil invalidate check

There is no separate stencil on gen < 6. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c | 16 +++- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_stat

[Mesa-dev] [v2 5/7] i965: Drop depth/stencil miptree pointers in alignment workaround

In brw_workaround_depthstencil_alignment() corresponding renderbuffers are always set to refer to the same temp miptrees. There is no need to carry them in context. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h| 3 --- src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 1/3] i965/miptree: Clarify face/level/layer in slice copy

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 39 ++- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 4b58268

[Mesa-dev] [PATCH 3/3] i965/gen4: Add support for single layer in alignment workaround

teximage 2d_array.ilkm64 ext_texture_array.copyteximage 1d_array.ilkm64 arb_texture_cube_map.copyteximage cube.ilkm64 CC: Kenneth Graunke CC: Jason Ekstrand CC: Ian Romanick Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_draw.c | 51 src/mesa

[Mesa-dev] [PATCH 2/3] i965/miptree: Separate src and dst slice specifiers in slice copy

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 60 --- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index f8fdde7

[Mesa-dev] [PATCH 03/15] i965/miptree: Add isl surface

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 7acfcb87a4..8479b285cb 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [PATCH 05/15] i965: Prepare image validation for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 061860cdf6..f44bac988f 100644 --- a/src/mesa

[Mesa-dev] [PATCH 02/15] i965: Add helper for converting isl tiling to bufmgr tiling

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_blit.h | 13 + 1 file changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h index 2604417e2d..5e4d1f5eb4 100644 --- a/src/mesa/drivers/dri/i965

[Mesa-dev] [PATCH 07/15] i965: Prepare framebuffer validator for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_fbo.c | 33 ++--- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 478e7b8884..e49f6df408 100644

[Mesa-dev] [PATCH 14/15] i965/miptree: Prepare range getter for isl based

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index ecb9186715..e2de4df498 100644 --- a

[Mesa-dev] [PATCH 08/15] i965/tex: Prepare image update for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_tex_image.c | 19 --- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index ea166f019f..b1fe8dd584 100644

[Mesa-dev] [PATCH 01/15] i965/miptree: Refactor mapping table alloc

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 253d833b13

[Mesa-dev] [PATCH 09/15] i965: Prepare slice copy for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 +-- 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index f44bac988f

[Mesa-dev] [PATCH 12/15] i965/blorp: Prepare for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 355f936f06..fee7c43d2c 100644 --- a/src/mesa/drivers/dri

[Mesa-dev] [PATCH 15/15] i965/gen6: Use isl for stencil surfaces

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_depth_state.c | 31 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++ 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c b/src/mesa

[Mesa-dev] [PATCH 04/15] i965: Prepare up/downsampling for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 ++- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 78a223a7f3

[Mesa-dev] i965/gen6: Represent stencil surfaces using isl

This is part of earlier work in the list. Major difference is that everything is now rebased on the new "side-by-side" stencil layout. Topi Pohjolainen (15): i965/miptree: Refactor mapping table alloc i965: Add helper for converting isl tiling to bufmgr tiling i965/miptree: Add i

[Mesa-dev] [PATCH 06/15] i965: Prepare slice validator for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index 8479b285cb..0b85bc12ef 100644 --- a

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