[Mesa-dev] [PATCH 11/19] st/mesa: add compute shader states

Changes from v2: - use as much common code as possible (eg. st_basic_variant) Signed-off-by: Samuel Pitoiset Reviewed-by: Marek Olšák (v1) Reviewed-by: Ilia Mirkin (v1) --- src/mesa/state_tracker/st_atom.c| 2 +- src/mesa/state_tracker/st_atom.h| 1 + src/mesa/state_tracker

Re: [Mesa-dev] [PATCH v3 00/19] add compute shaders support

On Wed, Feb 10, 2016 at 7:10 PM, Samuel Pitoiset wrote: Hi, This series adds the core support for ARB_compute_shader which is required for OpenGL 4.3. This series is now based on mesa master since Ilia has pushed his work related to ssbo+atomics. In piglit, this passes all compute related tests

[Mesa-dev] [PATCH v2 1/2] glsl: add missing types for buffer images

Spotted while trying to run dEQP tests related to ARB_shader_image_load_store. v2: fix index in names array Signed-off-by: Samuel Pitoiset Cc: Samuel Iglesias Gonsálvez --- src/compiler/glsl/ast_to_hir.cpp | 21 - 1 file changed, 12 insertions(+), 9 deletions(-) diff

[Mesa-dev] [PATCH 1/2] tgsi: fix out of bounds access in exec_atomop()

The number of channels must be 4 for all RGBA components. Fixes: 22d129601 ("tgsi: add support for image operations to tgsi_exec. (v2.1)") Signed-off-by: Samuel Pitoiset Cc: Dave Airlie --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Mesa-dev] [PATCH 2/2] tgsi: silence compiler warning in fetch_sampler_unit()

The unit variable can be used uninitialized. Fixes: 24e77cb09 ("tgsi: handle indirect sampler arrays. (v2)") Signed-off-by: Samuel Pitoiset Cc: Dave Airlie --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxi

[Mesa-dev] [PATCH v2 01/13] nvc0: bind driver cb for compute on c7[] for Kepler

ore. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 6 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 11 --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 40 - src/gallium/drivers/nouveau/nvc0/nve4_compute.h |

[Mesa-dev] [PATCH v2 02/13] nvc0: bind shader buffers for compute on Kepler

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +-- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 38 + 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src

[Mesa-dev] [PATCH v2 03/13] nvc0: bind user uniforms for compute on Kepler

Uniform buffer objects will be sticked to the driver constant buffer like buffers because the launch descriptor only allows 8 CBs. Input kernel parameters for OpenCL are still uploaded to screen->parm which is bound on c0, but this will be changed later with a new series. Signed-off-by: Sam

[Mesa-dev] [PATCH v2 04/13] nvc0: reserve an area for ubos info in the driver constbuf

The compute launch descriptor only allows to set up 8 CBs, but OpenGL requires at least 12 UBOs. To bypass this limitation, we store the ubos info into the driver constant buffer. This will be only used for Kepler. This bumps the size of each shader area from 1K to 2K. Signed-off-by: Samuel

[Mesa-dev] [PATCH v2 10/13] nvc0/ir: add atomics support on shared memory for Kepler

Signed-off-by: Samuel Pitoiset --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 114 - .../nouveau/codegen/nv50_ir_lowering_nvc0.h| 1 + 2 files changed, 114 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0

[Mesa-dev] [PATCH v2 12/13] nvc0: bump the maximum number of UBOs for compute on Kepler

The maximum number of uniform blocks (MAX_COMPUTE_UNIFORM_BLOCKS) per compute program must be at least 12. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 -- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 - 2 files changed, 3 deletions(-) diff --git

[Mesa-dev] [PATCH v2 11/13] nvc0/ir: do not lower shared+atomics on GM107+

For Maxwell, the ATOMS instruction can be used to perform atomic operations on shared memory instead of this load/store lowering pass. Signed-off-by: Samuel Pitoiset --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp| 20 +--- 1 file changed, 13 insertions(+), 7 deletions

[Mesa-dev] [PATCH v2 07/13] nvc0: add indirect compute support on Kepler

whole descriptor and overwrite a few bits Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 99 + 1 file changed, 67 insertions(+), 32 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouvea

[Mesa-dev] [PATCH v2 13/13] nvc0: enable compute shaders on GK104 and GM107+

Compute support on GK110 is still unstable for weird reasons, but this can be fixed later as the NVF0_COMPUTE envvar prevent using compute. Note that GL3.txt is not updated yet because GL_ARB_compute_shader is a bit useless without ARB_shader_image_load_store. Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH v2 08/13] nvc0/ir: add support for compute UBOs on Kepler

Make sure to avoid out of bounds access in presence of indirect array indexing by loading the size from the driver constant buffer. Signed-off-by: Samuel Pitoiset --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 55 +- .../nouveau/codegen/nv50_ir_lowering_nvc0.h

[Mesa-dev] [PATCH v2 09/13] nvc0/ir: fix wrong pred emission for ld lock on GK104

This fixes 84b9b8f (nvc0/ir: add missing emission of locked load predicate). Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0

[Mesa-dev] [PATCH v2 05/13] nvc0: store ubo info to the driver constbuf on Kepler

Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 3 +++ src/gallium/drivers/nouveau/nvc0/nvc0_program.c| 1 + src/gallium/drivers/nouveau/nvc0/nve4_compute.c| 26 +- 4

[Mesa-dev] [PATCH v2 06/13] nvc0: reduce likelihood of collision for real buffers on Kepler

Reduce likelihood of collision with real buffers by placing the hole at the top of the 4G area. This fixes some indirect draw+compute tests with large buffers. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 4 ++-- 1 file changed

[Mesa-dev] [PATCH v2 00/13] nvc0: ARB_compute_shader for Kepler/Maxwell

seful without images support. ARB_shader_image_load_store and ARB_shader_image_size are in work in progress and should be ready in a couple of weeks. Please review, Thanks! Samuel Pitoiset (13): nvc0: bind driver cb for compute on c7[] for Kepler nvc0: bind shader buffers for compute on Kepler

Re: [Mesa-dev] [PATCH v2 00/13] nvc0: ARB_compute_shader for Kepler/Maxwell

On 03/31/2016 06:27 PM, Ilia Mirkin wrote: On Thu, Mar 31, 2016 at 12:08 PM, Samuel Pitoiset wrote: Hi, This series adds support for ARB_compute_shader on GK104 and GM107+, except on GK110 where one test miserably fail (related to texelFetch) for really weird reasons. Anyway, this is not

Re: [Mesa-dev] [PATCH v2 01/13] nvc0: bind driver cb for compute on c7[] for Kepler

or fs ? Because msInfoBase is set to 0 for 3d. For compute, they are used in NVC0LoweringPass::adjustCoordinatesMS() which is called from processSurfaceCoordsNVE4(), so I think they are useful for compute. :-) On Mar 31, 2016 12:09 PM, "Samuel Pitoiset" mailto:samuel.pitoi...@gm

Re: [Mesa-dev] [PATCH v2 04/13] nvc0: reserve an area for ubos info in the driver constbuf

ned to 0x40 and I don't have enough free space to put ubos info. On Mar 31, 2016 12:09 PM, "Samuel Pitoiset" mailto:samuel.pitoi...@gmail.com>> wrote: The compute launch descriptor only allows to set up 8 CBs, but OpenGL requires at least 12 UBOs. To bypass this li

Re: [Mesa-dev] [PATCH v2 07/13] nvc0: add indirect compute support on Kepler

On 04/01/2016 07:34 AM, Ilia Mirkin wrote: On Mar 31, 2016 12:09 PM, "Samuel Pitoiset" mailto:samuel.pitoi...@gmail.com>> wrote: > > The grid size is stored as three 32-bits integers in the indirect > buffer but the launch descriptor uses a 32-bits integer

Re: [Mesa-dev] [PATCH v2 08/13] nvc0/ir: add support for compute UBOs on Kepler

On 04/01/2016 07:40 AM, Ilia Mirkin wrote: On Mar 31, 2016 12:09 PM, "Samuel Pitoiset" mailto:samuel.pitoi...@gmail.com>> wrote: > > Make sure to avoid out of bounds access in presence of indirect > array indexing by loading the size from the driver constant bu

Re: [Mesa-dev] [PATCH v2 11/13] nvc0/ir: do not lower shared+atomics on GM107+

On 04/01/2016 07:44 AM, Ilia Mirkin wrote: On Mar 31, 2016 12:09 PM, "Samuel Pitoiset" mailto:samuel.pitoi...@gmail.com>> wrote: > > For Maxwell, the ATOMS instruction can be used to perform atomic > operations on shared memory instead of this load/store lowering

[Mesa-dev] [PATCH v3 00/12] nvc0: ARB_compute_shader for Kepler/Maxwell

seful without images support. ARB_shader_image_load_store and ARB_shader_image_size are in work in progress and should be ready in a couple of weeks. Please review, Thanks! Samuel Pitoiset (12): nvc0: bind driver cb for compute on c7[] for Kepler nvc0: bind shader buffers for compute on Kepler

[Mesa-dev] [PATCH v3 05/12] nvc0: reduce likelihood of collision for real buffers on Kepler

Reduce likelihood of collision with real buffers by placing the hole at the top of the 4G area. This fixes some indirect draw+compute tests with large buffers. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 4 ++-- 1 file changed

[Mesa-dev] [PATCH v3 08/12] nvc0/ir: fix wrong pred emission for ld lock on GK104

This fixes 84b9b8f (nvc0/ir: add missing emission of locked load predicate). Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0

[Mesa-dev] [PATCH v3 02/12] nvc0: bind shader buffers for compute on Kepler

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +-- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 38 + 2 files changed, 39 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src

[Mesa-dev] [PATCH v3 09/12] nvc0/ir: add atomics support on shared memory for Kepler

Signed-off-by: Samuel Pitoiset --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 114 - .../nouveau/codegen/nv50_ir_lowering_nvc0.h| 1 + 2 files changed, 114 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0

[Mesa-dev] [PATCH v3 06/12] nvc0: add indirect compute support on Kepler

issing nouveau_pushbuf_space() Changes from v2: - upload the whole descriptor and overwrite a few bits Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 100 1 file changed, 68 insertions(+), 32 deletions(-) diff --git a/src/gallium/drivers/n

[Mesa-dev] [PATCH v3 03/12] nvc0: bind user uniforms for compute on Kepler

Uniform buffer objects will be sticked to the driver constant buffer like buffers because the launch descriptor only allows 8 CBs. Input kernel parameters for OpenCL are still uploaded to screen->parm which is bound on c0, but this will be changed later with a new series. Signed-off-by: Sam

[Mesa-dev] [PATCH v3 12/12] nvc0: enable compute shaders on GK104 and GM107+

Compute support on GK110 is still unstable for weird reasons, but this can be fixed later as the NVF0_COMPUTE envvar prevent using compute. Note that GL3.txt is not updated yet because GL_ARB_compute_shader is a bit useless without ARB_shader_image_load_store. Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH v3 07/12] nvc0/ir: add support for compute UBOs on Kepler

Make sure to avoid out of bounds access in presence of indirect array indexing by loading the size from the driver constant buffer. Changes from v2: - add a todo for clamping the offset to the max possible const buf - rework the lowering pass Signed-off-by: Samuel Pitoiset --- .../nouveau

[Mesa-dev] [PATCH v3 04/12] nvc0: store ubo info to the driver constbuf on Kepler

Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_driver.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 3 +++ src/gallium/drivers/nouveau/nvc0/nvc0_program.c| 1 + src/gallium/drivers/nouveau/nvc0/nve4_compute.c| 26 +- 4

[Mesa-dev] [PATCH v3 10/12] nvc0/ir: do not lower shared+atomics on GM107+

For Maxwell, the ATOMS instruction can be used to perform atomic operations on shared memory instead of this load/store lowering pass. Changes from v2: - remove one branch Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 17 ++--- 1 file

[Mesa-dev] [PATCH v3 11/12] nvc0: bump the maximum number of UBOs for compute on Kepler

The maximum number of uniform blocks (MAX_COMPUTE_UNIFORM_BLOCKS) per compute program must be at least 12. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 -- src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 - 2 files changed, 3 deletions(-) diff --git

[Mesa-dev] [PATCH v3 01/12] nvc0: bind driver cb for compute on c7[] for Kepler

ore. Changes from v2: - move ms and grid offsets after tex Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 6 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 11 --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 40 -

[Mesa-dev] [PATCH v4 06/12] nvc0: add indirect compute support on Kepler

- move nouveau_pushbuf_space() before the begin Changes from v3: - add missing nouveau_pushbuf_space() Changes from v2: - upload the whole descriptor and overwrite a few bits Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 111 1 file chang

Re: [Mesa-dev] [PATCH 19/20] mesa/st: enable compute shaders if images are also supported

Reviewed-by: Samuel Pitoiset On 04/02/2016 03:11 PM, Bas Nieuwenhuizen wrote: Signed-off-by: Bas Nieuwenhuizen --- src/mesa/state_tracker/st_extensions.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa

[Mesa-dev] [PATCH] nv50/ir: fix envyas variants when building the code lib

nvc0 and nve4 have been respectively replaced by gf100 and gk104. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/lib/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/lib/Makefile b/src/gallium/drivers

Re: [Mesa-dev] [PATCH] nv50: add edgeflag support when using inline vertex data submit

Ping? (~4 months later). Ilia? :) On 11/23/2015 09:36 PM, Samuel Pitoiset wrote: Fixes the following piglit tests: - gl-1.0-edgeflag - gl-1.0-edgeflag-quads - gl-2.0-edgeflag - gl-2.0-edgeflag-immediate - point-vertex-id divisor - point-vertex-id gl_InstanceID - point-vertex-id

Re: [Mesa-dev] [PATCH] nv50, nvc0: support sending string markers down into the command stream

I guess it's needed to override the gl version to use this feature as 4.3 is not yet supported? Anyway, this might be useful if apps use glDebugMessageInsert(). Reviewed-by: Samuel Pitoiset On 04/03/2016 10:04 PM, Ilia Mirkin wrote: This should hopefully make it a little easier to

[Mesa-dev] [PATCH] trace: add missing set_shader_images()

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/trace/tr_context.c| 39 ++ src/gallium/drivers/trace/tr_dump_state.c | 40 +++ src/gallium/drivers/trace/tr_dump_state.h | 2 ++ 3 files changed, 81 insertions(+) diff --git a/src

[Mesa-dev] [PATCH] nv50/ir: do not try to attach JOIN ops to ATOM

This might result in an INVALID_OPCODE dmesg error in case a join is attached to an atomic operation. Spotted with arb_shader_image_load_store-host-mem-barrier on GK104. Signed-off-by: Samuel Pitoiset Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen

Re: [Mesa-dev] [PATCH] nv50/ir: do not try to attach JOIN ops to ATOM

On 04/07/2016 10:46 PM, Ilia Mirkin wrote: On Thu, Apr 7, 2016 at 4:42 PM, Samuel Pitoiset wrote: This might result in an INVALID_OPCODE dmesg error in case a join is attached to an atomic operation. Spotted with arb_shader_image_load_store-host-mem-barrier on GK104. Signed-off-by: Samuel

Re: [Mesa-dev] [PATCH mesa v2 1/2] nouveau: codegen: Use FILE_MEMORY_BUFFER for buffers

On 04/08/2016 12:17 PM, Hans de Goede wrote: Hi, On 23-03-16 23:10, Samuel Pitoiset wrote: Are you sure this won't break compute shaders on fermi? Could you please double-check that? I just checked: lspci: 01:00.0 VGA compatible controller: NVIDIA Corporation GF119 [GeForce GT 610]

[Mesa-dev] [PATCH] nvc0: avoid tex read fault from compute shaders on GK110

regressions. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c index 4d069df..89e6187 100644 --- a/src/gallium

Re: [Mesa-dev] [PATCH] nouveau: Add missing PIPE_SHADER_CAP_INTEGERS to get_shader_param()

The prefix should be "nv30:" instead of "nouveau:" I guess. Reviewed-by: Samuel Pitoiset On 04/11/2016 02:13 PM, Hans de Goede wrote: Add missing PIPE_SHADER_CAP_INTEGERS for frag shaders to nv30_screen_get_shader_param(). Signed-off-by: Hans de Goede --- src/gallium/

[Mesa-dev] [RFC 00/24] nvc0: ARB_shader_image_load_store/size on GK104

store on GK104 Samuel Pitoiset (22): nvc0: add preliminary support for images nvc0: reserve an area for surfaces info in the driver constbuf nvc0: bind images on compute shaders for Kepler nvc0: bind images on 3D shaders for Kepler nvc0: compute correct image dimensions based on the targe

[Mesa-dev] [RFC 08/24] nvc0: enable RGB10_A2UI format on GK104

No clue why this was not enabled by default before, maybe because the SULDP conversion was wrong. Anyway, this helps in fixing all rgb10_a2ui piglit tests. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions

[Mesa-dev] [RFC 03/24] nvc0: bind images on compute shaders for Kepler

instead of pipe_surface. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.h | 5 ++- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 54 + src/gallium/drivers/nouveau/nvc0

[Mesa-dev] [RFC 01/24] nvc0: add preliminary support for images

by Ilia Mirkin. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.c| 17 +++ src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 4 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.h | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 53

[Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

Similar to surfaces validation for compute shaders. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 26 - 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/src

[Mesa-dev] [RFC 07/24] nvc0: shift address with blocksize for image buffers

This fixes a bunch of dEQP image buffers related tests. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c index d1240b4

[Mesa-dev] [RFC 02/24] nvc0: reserve an area for surfaces info in the driver constbuf

hader compile time. This bumps the size of each shader area from 1K to 2K. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_compute.c| 4 ++-- src/gallium/drivers/nouveau/nvc0/nvc0_context.h| 6 +++--- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +-

[Mesa-dev] [RFC 05/24] nvc0: compute correct image dimensions based on the target

Loosely based on softpipe but with some changes, this computes correct width, height and depth of different targets to help in processing coordinates from the codegen part. This fixes a ton of dEQP/piglit tests. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c

[Mesa-dev] [RFC 06/24] nvc0: fix address offset when images have multiple levels

This fixes arb_shader_image_load_store-level. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c index fa89324..d1240b4

[Mesa-dev] [RFC 12/24] nvc0/ir: fix constraints for OP_SUSTx on Kepler

Destination type is actually always 32-bits, so typeSizeof() returns 4 and no sources are condensed. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [RFC 21/24] nvc0: reduce GL_MAX_3D_TEXTURE_SIZE to 2048 on Kepler+

The blob sets it to 2048 and using 4096 reports an INVALID_DATA error with RT_ARRAY_MODE when z is 4096. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium

[Mesa-dev] [RFC 10/24] nv50/ir: add support for TGSI image declarations

Old and dead resource code will be removed once images are completely done. Based on original patch by Ilia Mirkin. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 27 +++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a

[Mesa-dev] [RFC 24/24] nvc0: expose GLSL version 420 on GK104

Other chipsets will be added later. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c index 2d22a50..3ba1e7a

[Mesa-dev] [RFC 09/24] nvc0: add missing glMemoryBarrier bits

This fixes a bunch of subtests of arb_shader_image_load_store-host-mem-barrier. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.c b/src

[Mesa-dev] [RFC 18/24] nvc0/ir: fix 1D arrays images for Kepler

For 1D arrays, the array index is stored in the Z component. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [RFC 19/24] nvc0/ir: add indirect support for images on Kepler

This fixes arb_shader_image_load_store-indexing and arb_shader_image_load_store-max-images. Signed-off-by: Samuel Pitoiset --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 42 +++--- 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/src/gallium/drivers

[Mesa-dev] [RFC 13/24] nv50/ir: enable early fragment test with explicit user control

.functional.image_load_store.early_fragment_tests.* tests. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen

[Mesa-dev] [RFC 11/24] nv50/ir: re-introduce TGSI lowering pass for images

This is loosely based on the previous lowering pass wrote by calim four years ago. I did clean the code and fixed some issues. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 155 - 1 file changed, 152 insertions(+), 3 deletions

[Mesa-dev] [RFC 14/24] nv50/ir: add OP_BUFQ for buffers query

TGSI RESQ allows both images and buffers but we have to make a distinction between these two type of resources in our lowering pass. Introducing OP_BUFQ which is a fake operand will allow to implement OP_SUQ for surfaces. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen

[Mesa-dev] [RFC 22/24] nvc0: inform users that 3D images are not fully supported

3D images are a bit more complicated to implement and will probably requires a bunch of headaches and we don't care for now because they do not seem to be really used by apps. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 3 ++- 1 file changed, 2 inser

[Mesa-dev] [RFC 23/24] nvc0: enable ARB_shader_image_load_store on GK104

From: Ilia Mirkin This exposes 8 images for all shader types. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0

[Mesa-dev] [RFC 15/24] nv50/ir: make use of OP_SUQ for surfaces query

This implements RESQ for surfaces which comes from imageSize() GLSL bultin. As the dimensions are sticked into the driver constant buffer, this only has to be lowered with loads. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 28

[Mesa-dev] [RFC 17/24] nvc0/ir: fix cube images for Kepler

Like 2d array images, the z-dimension needs to be clamped. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0

[Mesa-dev] [RFC 20/24] nvc0/ir: prevent out of bounds when no images are bound

Checking if the image address is not 0 should be enough to prevent read faults. To improve robustness, make sure that the destination value of atomic operations is correctly initialized in case the instruction is not performed. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen

Re: [Mesa-dev] [RFC 03/24] nvc0: bind images on compute shaders for Kepler

On 04/13/2016 03:38 AM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: Old surfaces validation code will be removed once images are completely done for Fermi/Kepler, that explains why I only disable it for now. set_surface_info() which sticks surfaces information

[Mesa-dev] [PATCH] nvc0: allow to use compute support on GM200

This works like a charm but please not that NVF0_COMPUTE have to be set because compute support is still not enabled by default on GK110+. This will require more testing to make sure it won't break the 3D state. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv_object.

[Mesa-dev] [PATCH] nvc0: do not break the universe on GK110+

I removed that return 0 by mistake. Ooops. Fixes: 6e23fd4 ("nvc0: allow to use compute support on GM200") Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_scree

Re: [Mesa-dev] [RFC 01/24] nvc0: add preliminary support for images

On 04/14/2016 07:48 PM, Pierre Moreau wrote: On 01:56 AM - Apr 13 2016, Samuel Pitoiset wrote: This implements set_shader_images() and resource invalidation for images. As OpenGL requires at least 8 images, we are going to expose this minimum value even if this might be raised for Kepler, but

Re: [Mesa-dev] [RFC 03/24] nvc0: bind images on compute shaders for Kepler

On 04/13/2016 10:11 PM, Ilia Mirkin wrote: On Wed, Apr 13, 2016 at 11:26 AM, Samuel Pitoiset wrote: On 04/13/2016 03:38 AM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: Old surfaces validation code will be removed once images are completely done for Fermi

Re: [Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

On 04/13/2016 10:14 PM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: Similar to surfaces validation for compute shaders. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- src/gallium/drivers/nouveau/nvc0

Re: [Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

On 04/14/2016 08:03 PM, Pierre Moreau wrote: On 01:56 AM - Apr 13 2016, Samuel Pitoiset wrote: Similar to surfaces validation for compute shaders. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c

Re: [Mesa-dev] [RFC 05/24] nvc0: compute correct image dimensions based on the target

On 04/13/2016 10:23 PM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: Loosely based on softpipe but with some changes, this computes correct width, height and depth of different targets to help in processing coordinates from the codegen part. This fixes a ton of

Re: [Mesa-dev] [RFC 09/24] nvc0: add missing glMemoryBarrier bits

Fine by me. -ilia On Tue, Apr 12, 2016 at 7:56 PM, Samuel Pitoiset wrote: This fixes a bunch of subtests of arb_shader_image_load_store-host-mem-barrier. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 9 - 1 file changed, 8 insertions

Re: [Mesa-dev] [RFC 11/24] nv50/ir: re-introduce TGSI lowering pass for images

On 04/13/2016 10:27 PM, Ilia Mirkin wrote: The .raw stuff is never true. I'd just kill it off for now. Okay. On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: This is loosely based on the previous lowering pass wrote by calim four years ago. I did clean the code and fixed

Re: [Mesa-dev] [RFC 18/24] nvc0/ir: fix 1D arrays images for Kepler

On 04/13/2016 10:39 PM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: For 1D arrays, the array index is stored in the Z component. Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 17 + 1 file

Re: [Mesa-dev] [RFC 20/24] nvc0/ir: prevent out of bounds when no images are bound

On 04/13/2016 10:44 PM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: Checking if the image address is not 0 should be enough to prevent read faults. To improve robustness, make sure that the destination value of atomic operations is correctly initialized in case

Re: [Mesa-dev] [RFC 24/24] nvc0: expose GLSL version 420 on GK104

rate patch. On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: Other chipsets will be added later. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/s

Re: [Mesa-dev] [RFC 15/24] nv50/ir: make use of OP_SUQ for surfaces query

On 04/13/2016 10:33 PM, Ilia Mirkin wrote: On Tue, Apr 12, 2016 at 7:57 PM, Samuel Pitoiset wrote: This implements RESQ for surfaces which comes from imageSize() GLSL bultin. As the dimensions are sticked into the driver constant buffer, this only has to be lowered with loads. Signed-off-by

Re: [Mesa-dev] [RFC 04/24] nvc0: bind images on 3D shaders for Kepler

On 04/15/2016 09:41 AM, Hans de Goede wrote: Hi, On 15-04-16 00:01, Samuel Pitoiset wrote: On 04/14/2016 08:03 PM, Pierre Moreau wrote: On 01:56 AM - Apr 13 2016, Samuel Pitoiset wrote: Similar to surfaces validation for compute shaders. Signed-off-by: Samuel Pitoiset --- src/gallium

Re: [Mesa-dev] [PATCH] st/mesa: Use correct size for compute CAPs.

Reviewed-by: Samuel Pitoiset On 04/20/2016 03:35 PM, Bas Nieuwenhuizen wrote: Some CAPs are stored as 64-bit value while Mesa stores the related constant as 32-bit value. Signed-off-by: Bas Nieuwenhuizen --- src/mesa/state_tracker/st_extensions.c | 8 ++-- 1 file changed, 6 insertions

Re: [Mesa-dev] [PATCH 1/4] gallium: add bool return to pipe_context::end_query

Yeah, this makes sense. Reviewed-by: Samuel Pitoiset On 04/20/2016 05:43 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle Even when begin_query succeeds, there can still be failures in query handling. For example for radeon, additional buffers may have to be allocated when queries span

Re: [Mesa-dev] [PATCH 2/4] st/mesa: check return value of begin/end_query

On 04/20/2016 05:43 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle They can only indicate out of memory conditions, since the other error conditions are caught earlier. --- src/mesa/state_tracker/st_cb_queryobj.c | 55 - 1 file changed, 33 insertions(+), 22

[Mesa-dev] [PATCH 1/2] gk110/ir: make use of IMUL32I for all immediates

Signed-off-by: Samuel Pitoiset Cc: "11.1 11.2" --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_

[Mesa-dev] [PATCH 2/2] gk110/ir: use separate signed expressions for dst/src with IMUL32I

Forcing the destination type to be signed when the source is signed is not totally correct. Signed-off-by: Samuel Pitoiset Cc: "11.1 11.2" --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/galli

[Mesa-dev] [PATCH] gk110/ir: do not overwrite def value with zero for EXCH ops

This is only valid for other atomic operations (including CAS). This fixes an invalid opcode error from dmesg. While we are it, make sure to initialize global addr to 0 for other atomic operations. Signed-off-by: Samuel Pitoiset Cc: "11.1 11.2" --- .../drivers/nouve

Re: [Mesa-dev] [PATCH] gk110/ir: do not overwrite def value with zero for EXCH ops

003fe */ On Wed, Apr 20, 2016 at 1:47 PM, Samuel Pitoiset wrote: This is only valid for other atomic operations (including CAS). This fixes an invalid opcode error from dmesg. While we are it, make sure to initialize global addr to 0 for other atomic operations. Signed-off-by: Samuel

Re: [Mesa-dev] [PATCH 2/2] gk110/ir: use separate signed expressions for dst/src with IMUL32I

ed expressions for dst/src are separated. -ilia On Wed, Apr 20, 2016 at 1:06 PM, Samuel Pitoiset wrote: Forcing the destination type to be signed when the source is signed is not totally correct. Signed-off-by: Samuel Pitoiset Cc: "11.1 11.2" --- src/gallium/drivers/nouvea

Re: [Mesa-dev] [PATCH 2/4] st/mesa: check return value of begin/end_query

On 04/20/2016 09:37 PM, Nicolai Hähnle wrote: On 20.04.2016 11:13, Samuel Pitoiset wrote: On 04/20/2016 05:43 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle They can only indicate out of memory conditions, since the other error conditions are caught earlier. --- src/mesa/state_tracker

[Mesa-dev] [PATCH 5/7] gk110/ir: add emission for VSHL

Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 58 ++ 1 file changed, 58 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index 15280df

[Mesa-dev] [PATCH 0/7] nvc0: ARB_shader_image_load_store/size on GK110

Hi, This series is based on the previous one for GK104. Between GK104 and GK110 only the ISA has changed. This adds code emission for all instructions that are needed to support surfaces/images. I have exactly the same passrate for both deqp and piglit as GK104. Please review, Thanks! Samuel

[Mesa-dev] [PATCH 3/7] gk110/ir: add emission for OP_SULDB and OP_SUSTx

Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 153 + 1 file changed, 153 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index

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