For Maxwell, the ATOMS instruction can be used to perform atomic
operations on shared memory instead of this load/store lowering pass.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
---
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 20 +++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 7e6c87a..83e753e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1294,10 +1294,14 @@ NVC0LoweringPass::handleATOM(Instruction *atom)
sv = SV_LBASE;
break;
case FILE_MEMORY_SHARED:
- if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
- handleSharedATOMNVE4(atom);
- } else {
- handleSharedATOM(atom);
+ if (targ->getChipset() < NVISA_GM107_CHIPSET) {
+ // For Fermi/Kepler, we have to use ld lock/st unlock to perform
+ // atomic operations on shared memory. For Maxwell, ATOMS is enough.
+ if (targ->getChipset() >= NVISA_GK104_CHIPSET) {
+ handleSharedATOMNVE4(atom);
+ } else {
+ handleSharedATOM(atom);
+ }
}
return true;
default:
@@ -1326,9 +1330,11 @@ NVC0LoweringPass::handleATOM(Instruction *atom)
bool
NVC0LoweringPass::handleCasExch(Instruction *cas, bool needCctl)
{
- if (cas->src(0).getFile() == FILE_MEMORY_SHARED) {
- // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
- return false;
+ if (targ->getChipset() < NVISA_GM107_CHIPSET) {
+ if (cas->src(0).getFile() == FILE_MEMORY_SHARED) {
+ // ATOM_CAS and ATOM_EXCH are handled in handleSharedATOM().
+ return false;
+ }
}
if (cas->subOp != NV50_IR_SUBOP_ATOM_CAS &&
--
2.7.4
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