This patch is
Reviewed-by: Rafael Antognolli
On Wed, Apr 25, 2018 at 09:23:04AM -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> v2: Branding changed
>
> Signed-off-by: Matt Atwood
> ---
> include/pci_ids/i965_pci_ids.h | 1 +
> 1 file changed,
On Tue, Apr 24, 2018 at 05:48:44PM -0700, Nanley Chery wrote:
> Reduce complexity and allow the next patch to delete some code. With
> this change, clear operations will still be skipped and setting the
> aux_state will cause no side-effects.
It's going to skip the fast clear, but if I understood
This patch is
Reviewed-by: Rafael Antognolli
On Tue, Apr 24, 2018 at 05:48:42PM -0700, Nanley Chery wrote:
> Split out this functionality to enable a fast-clear optimization for
> color miptrees in the next commit.
>
> v2: Avoid the additional refactor (Jason).
> ---
> sr
On Wed, Apr 25, 2018 at 11:40:15AM -0700, Nanley Chery wrote:
> On Wed, Apr 25, 2018 at 11:30:14AM -0700, Rafael Antognolli wrote:
> > On Tue, Apr 24, 2018 at 05:48:44PM -0700, Nanley Chery wrote:
> > > Reduce complexity and allow the next patch to delete some code. With
> &
And pushed.
Thanks,
Rafael
On Wed, Apr 25, 2018 at 09:49:45AM -0700, Rafael Antognolli wrote:
> This patch is
>
> Reviewed-by: Rafael Antognolli
>
> On Wed, Apr 25, 2018 at 09:23:04AM -0700, matthew.s.atw...@intel.com wrote:
> > From: Matt Atwood
> >
> > v2:
you don't want to. We can just send a new one later clarifying these
points, and we could also update the comment where the resolve happens
to clarify that it should only happen to layers not being cleared now.
In any case, this patch is a nice cleanup.
Reviewed-by: Rafael Antognolli
>
On Wed, Apr 25, 2018 at 02:53:26PM -0700, Nanley Chery wrote:
> On Wed, Apr 25, 2018 at 02:26:18PM -0700, Rafael Antognolli wrote:
> > On Tue, Apr 24, 2018 at 05:48:45PM -0700, Nanley Chery wrote:
> > > Determine the predicate for updating the indirect depth value in the
> &g
On Thu, Apr 26, 2018 at 10:41:37AM -0700, Nanley Chery wrote:
> On Wed, Apr 25, 2018 at 08:53:36PM -0400, Jason Ekstrand wrote:
> >
> >
> > On April 25, 2018 20:25:16 Nanley Chery wrote:
> >
> > On Wed, Apr 25, 2018 at 04:50:11PM -0700, Jason Ekstrand wrote:
> > On Tue, Apr 24, 2018 at 5:48 PM,
On Wed, May 09, 2018 at 03:08:03PM +0100, Lionel Landwerlin wrote:
> It's just not possible to have a device with no subslices.
Reviewed-by: Rafael Antognolli
> CID: 1433511
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/dev/gen_device_info.c | 1 +
> 1 fi
In the summary log, you should drop the mention to post sync operation
too, and mention stall on pixel scoreboard, right?
With that, this and the next patches are
Reviewed-by: Rafael Antognolli
On Wed, May 09, 2018 at 12:39:51AM +0100, Lionel Landwerlin wrote:
> Invalidating the indirect st
It looks like we can't rely on the simulator to always translate virtual
addresses to physical ones correctly. So let's use physical everywhere.
Since our current GGTT maps virtual to physical addresses in a 1:1 way,
no further changes are required.
Additionally, we have other address spaces not
Hopefully it's a little more descriptive, and more accurate.
Cc: Lionel Landwerlin
---
src/intel/tools/aub_write.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c
index e92bdaf5ed4..5d59b4ef28a 100644
--- a/src/intel/t
On Wed, Aug 08, 2018 at 11:11:11PM +0100, Lionel Landwerlin wrote:
> On 08/08/18 20:07, Rafael Antognolli wrote:
> > On Tue, Aug 07, 2018 at 06:35:18PM +0100, Lionel Landwerlin wrote:
> > > When we map a PPGTT buffer into a continous address space of aubinator
> > > t
ge (adding new tests for
some new cases we have now), but the series seems reasonable imho to
start getting some review already.
Cc: Jason Ekstrand
Rafael Antognolli (14):
anv/tests: Fix block_pool_no_free test.
anv/allocator: Add anv_state_table.
anv/allocator: Use anv_state_table on
We will need specially the anv_block_pool_map, to find the
map relative to some BO that is not at the start of the block pool.
---
src/intel/vulkan/anv_allocator.c | 23 ---
src/intel/vulkan/anv_batch_chain.c | 5 +++--
src/intel/vulkan/anv_private.h | 7 +++
src/in
It's possible that we still have some space left in the block pool, but
we try to allocate a state larger than that state. This means such state
would start somewhere within the range of the old block_pool, and end
after that range, within the range of the new size.
That's fine when we use userptr
They won't be true anymore once we add support for multiple BOs with
non-userptr.
---
src/intel/vulkan/genX_gpu_memcpy.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/intel/vulkan/genX_gpu_memcpy.c
b/src/intel/vulkan/genX_gpu_memcpy.c
index 1bee1c6dc17..e20179fa675 100644
--- a/src/in
Maybe we should already rename anv_free_list2 -> anv_free_list since the
old one is gone.
---
src/intel/vulkan/anv_allocator.c | 55
src/intel/vulkan/anv_private.h | 11 ---
2 files changed, 66 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src
The test was checking whether -1 was smaller than an unsigned int, which
is always false. So it was exiting early and never running until the
end, since it would reach the condition (thread_max == -1).
However, just fixing that is not enough. The test is currently getting
the highest block on each
---
src/intel/vulkan/anv_allocator.c | 32 ++--
src/intel/vulkan/anv_private.h | 2 +-
2 files changed, 19 insertions(+), 15 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 5f0458afd77..2171a97970b 100644
--- a/src
Change block_pool->bo to be a pointer, and update its usage everywhere.
This makes it simpler to switch it later to a list of BOs.
---
src/intel/vulkan/anv_allocator.c | 31 +++---
src/intel/vulkan/anv_batch_chain.c | 8
src/intel/vulkan/anv_blorp.c | 2 +
TODO: This is just flushing the entire dynamic states on every execbuf.
Maybe it's too much. However, in theory we should be already flushing
the states as needed, but I think we didn't hit any bug due to the
coherence implied by userptr.
---
src/intel/vulkan/anv_batch_chain.c | 4
1 file cha
This commit tries to rework the code that split and returns chunks back
to the state pool, while still keeping the same logic.
The original code would get a chunk larger than we need and split it
into pool->block_size. Then it would return all but the first one, and
would split that first one into
We now have multiple BOs in the block pool, but sometimes we still
reference only the first one in some instructions, and use relative
offsets in others. So we must be sure to add all the BOs from the block
pool to the validation list when submitting commands.
---
src/intel/vulkan/anv_batch_chain.
Add a structure to hold anv_states. This table will initially be used to
recicle anv_states, instead of relying on a linked list implemented in
GPU memory. Later it could be used so that all anv_states just point to
the content of this struct, instead of making copies of anv_states
everywhere.
TOD
If softpin is supported, create new BOs for the required size and add the
respective BO maps. The other main change of this commit is that
anv_block_pool_map() now returns the map for the BO that the given
offset is part of. So there's no block_pool->map access anymore (when
softpin is used.
---
s
Usage of anv_state_table_add is really annoying, see comment on the
previous commit.
---
src/intel/vulkan/anv_allocator.c | 96 +---
src/intel/vulkan/anv_private.h | 4 +-
2 files changed, 67 insertions(+), 33 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator
So far we use only one BO (the last one created) in the block pool. When
we switch to not use the userptr API, we will need multiple BOs. So add
code now to store multiple BOs in the block pool.
This has several implications, the main one being that we can't use
pool->map as before. For that reaso
On Mon, Dec 10, 2018 at 12:45:00PM -0600, Jason Ekstrand wrote:
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> We will need specially the anv_block_pool_map, to find the
> map relative to some BO that is not at the start of the block pool.
> --
On Mon, Dec 10, 2018 at 04:56:40PM -0600, Jason Ekstrand wrote:
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> This commit tries to rework the code that split and returns chunks back
> to the state pool, while still keeping the same logic.
>
>
On Mon, Dec 10, 2018 at 11:10:02PM -0600, Jason Ekstrand wrote:
>
>
> On Mon, Dec 10, 2018 at 5:48 PM Rafael Antognolli
>
> wrote:
>
> On Mon, Dec 10, 2018 at 04:56:40PM -0600, Jason Ekstrand wrote:
> > On Fri, Dec 7, 2018 at 6:06 PM Rafael Antogn
e missing some flushes in the states allocated in
anv_shader_bin_create(). I added them there and apparently I don't need
this patch anymore.
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> TODO: This is just flushing the entire dynamic states on every exe
On Mon, Dec 10, 2018 at 01:49:43PM -0600, Jason Ekstrand wrote:
> On Fri, Dec 7, 2018 at 6:06 PM Rafael Antognolli
> wrote:
>
> We now have multiple BOs in the block pool, but sometimes we still
> reference only the first one in some instructions, and use relative
>
On Wed, Oct 31, 2018 at 04:27:31PM -0700, Kenneth Graunke wrote:
> On Wednesday, October 31, 2018 11:15:28 AM PDT Rafael Antognolli wrote:
> > On Tue, Oct 30, 2018 at 04:32:54PM -0700, Kenneth Graunke wrote:
> > > On Monday, October 29, 2018 10:19:54 AM PDT Rafael Antognolli
x27;t remember the details of how, though.
Anyway, this looks better, and I assume it doesn't break anything.
Reviewed-by: Rafael Antognolli
> Fixes: 92eb5bbc68d7 "intel/blorp: Only copy clear color when doing..."
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=10
don't think it's whitelisted by the kernel either, it's just writable).
I'm seeing it being disabled at WaDisable3DMidCmdPreemption, seems to be
in effect since commit 5152defe4a53ad15e6d96c422440152302c8abd7.
And it's whitelisted by WaEnablePreemptionGranularityContro
On Tue, Feb 20, 2018 at 08:11:14AM -0800, Rafael Antognolli wrote:
> On Fri, Feb 16, 2018 at 06:37:55PM -0800, Ben Widawsky wrote:
> > On 18-02-16 13:44:00, Antognolli, Rafael wrote:
> > > "This field controls the granularity of the replay mechanism when
> > &g
On Wed, Jan 24, 2018 at 11:20:07AM +0200, Pohjolainen, Topi wrote:
> On Fri, Jan 19, 2018 at 11:54:37AM -0800, Rafael Antognolli wrote:
> > Some instructions contain fields that are either an address or a value
> > of some type based on the content of other fields, such as clear c
Makes sense to me, there's no need to keep copying the clear color for
every slice if we only fast clear the first one.
Reviewed-by: Rafael Antognolli
On Tue, Feb 20, 2018 at 03:08:11PM -0800, Jason Ekstrand wrote:
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 5 -
> 1 f
My understanding is that this commit is enough to make the driver try to
initialize, at least for i965. If that's the case, how about we add
something like what was removed by commit
bf1577fe0972ae910c071743dc89d261a46c2926 for CNL?
It could be either in this commit, or in a commit that precedes t
Tested-by: Rafael Antognolli
On Wed, Feb 21, 2018 at 01:08:26PM -0800, Jason Ekstrand wrote:
> It's true for depth HiZ clears because we only have HiZ on single-slice
> images right now. However, for stencil-only clears there is no such
> restriction.
> ---
> src/intel/vulk
The lower bits seem to have extra fields in every platform but gen8
(even though we don't use them in gen9). So just go ahead and avoid
using them for the address.
Signed-off-by: Rafael Antognolli
Reviewed-by: Topi Pohjolainen
---
src/intel/vulkan/anv_image.c
.
Signed-off-by: Rafael Antognolli
---
src/intel/isl/isl.h | 9 +
src/intel/isl/isl_surface_state.c | 18 ++
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index f1b38efed44..bab0ad3d544 100644
--- a
The size of the clear color struct (expected by the hardware) is 8
dwords (isl_dev.ss.clear_value_state_size here). But we still need to
track the size of the clear color, used when memcopying it to/from the
state buffer. For that we keep isl_dev.ss.clear_value_size.
Signed-off-by: Rafael
h the address. But if they are in the higher 32 bits, they get
discarded.
On Gen10 we have fields that share space with the higher 16 bits of the
address too. This commit makes sure those fields don't get discarded.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen_pack_header.py | 9 ++
t;Clear Color Address"
to "Clear Value Address" and use it for both color and depth. Do the
same for the high bits.
TODO: add support for multiple addresses at the same position in the
xml.
v2: Combine high and low order bits into a single address field.
Signed-off-by: Rafael Antogno
Rebase of this series after lots of aux surface changes on anv.
Cc: Jason Ekstrand
Cc: Jordan Justen
Cc: Topi Pohjolainen
Rafael Antognolli (13):
anv/image: Do not override lower bits of dword.
genxml: Preserve fields that share dword space with addresses.
intel/genxml: Use a single
later add the struct to the genxml, though it wouldn't
really be used for anything else other than calculating this size.
[jordan.l.jus...@intel.com: isl_device_init changes]
Signed-off-by: Rafael Antognolli
Signed-off-by: Jordan Justen
---
src/intel/isl/isl.c | 27 ++---
Store the default clear address for HiZ fast clears on a global bo, and
point to it when needed.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_device.c | 19 +++
src/intel/vulkan/anv_image.c | 10 +++---
src/intel/vulkan/anv_private.h | 1 +
3 files changed
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16
1 file changed, 16 insertions
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel/bl
On Gen10+, instead of copying the clear color from the state buffer to
the surface state, just use the address of the state buffer in the
surface state directly. This way we can avoid the copy from state buffer
to surface state.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_image.c
On Gen10, whenever the fast clear color changes, update it on the clear
color entry buffer. This allow us to use it directly when emitting the
surface state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 26 ++
1 file changed, 26 insertions
This warning showed up after aux_bo started being used inside
if (use_clear_address) {...
But use_clear_address depends on aux_surf being not null, in which case
aux_bo would also be set. Make the compiler happy anyway.
Signed-off-by: Rafael Antognolli
Reviewed-by: Nanley Chery
---
src/mesa
Similarly to vulkan where we store the clear value in the aux surface,
we can do the same in GL.
v2: Remove unneeded extra function.
v3: Use clear_value_state_size instead of clear_value_size.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 ++
1
On Mon, Feb 26, 2018 at 01:07:54PM -0800, Jordan Justen wrote:
> On 2018-02-21 13:45:14, Rafael Antognolli wrote:
> > The size of the clear color struct (expected by the hardware) is 8
> > dwords (isl_dev.ss.clear_value_state_size here). But we still need to
> > track the si
On Mon, Feb 26, 2018 at 05:04:37PM -0800, Jason Ekstrand wrote:
> On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli
> > wrote:
>
> The size of the clear color struct (expected by the hardware) is 8
> dwords (isl_dev.ss.clear_value_state_size here). But we still need
On Tue, Feb 27, 2018 at 11:46:12AM -0800, Jason Ekstrand wrote:
> On Tue, Feb 27, 2018 at 9:35 AM, Rafael Antognolli
> > wrote:
>
> On Mon, Feb 26, 2018 at 05:04:37PM -0800, Jason Ekstrand wrote:
> > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli <
>
On Tue, Feb 27, 2018 at 02:58:01PM -0800, Jason Ekstrand wrote:
> On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli
> > wrote:
>
> On Gen10+, instead of copying the clear color from the state buffer to
> the surface state, just use the address of the state buffer in
on, Feb 26, 2018 at 1:14 PM, Jordan Justen <
> > > jordan.l.jus...@intel.com>
> > > > wrote:
> > > >
> > > > > On 2018-02-21 13:45:15, Rafael Antognolli wrote:
> > > > > > + bool use_clear_address;
> > > > >
On Wed, Feb 28, 2018 at 02:15:19AM -0800, Jordan Justen wrote:
> On 2018-02-28 01:58:24, Samuel Iglesias Gonsálvez wrote:
> > What is the idea for src/intel/dev/ ?
> >
> > I'm not against this patch, just asking.
>
> Ken noticed a lot of duplicate lines in the xml for surface formats.
> (Patch 4)
This is matching both the kernel and the spec.
Reviewed-by: Rafael Antognolli .
On Wed, Feb 14, 2018 at 05:42:24PM -0800, Rodrigo Vivi wrote:
> Let's sync CNL ids with Spec and kernel.
>
> Sync with kernel commit '3f43031b1693 ("drm/i915/cnl:
> Add Cannonlake PCI
uint16_t eu_subslice_stride;
> + } topology;
> +
I wonder if such information shouldn't be stored in gen_device_info. But
it seems the rest of the OA code seems to be tied to i965 anyways, so I
guess this should be fine.
In any case, series is:
Acked-by: Rafael Antognolli
>
too (Jason, Jordan)
- Add field for Converted Clear Color to gen11 (Jason)
- Add clear_color_state_offset to differentiate from
clear_value_offset.
- Fix all the places where clear_value_size was used.
[jordan.l.jus...@intel.com: isl_device_init changes]
Signed-off-by: Rafael Antognolli
Signed
Extract the code from color_attachment_compute_aux_usage, so we can
later reuse it to update the clear color state buffer.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_private.h | 20
src/intel/vulkan/genX_cmd_buffer.c | 14 +-
2 files changed
.
Signed-off-by: Rafael Antognolli
---
src/intel/isl/isl.h | 9 +
src/intel/isl/isl_surface_state.c | 18 ++
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 2edf0522e32..c50b78d4701 100644
--- a
order to avoid
having both places doing that, I tried to centralize that code in
blorp.
- Now blorp updates the clear color whenever we are doing a fast clear
and have the clear_color_addr field set with a valid buffer.
Cc: Jason Ekstrand
Cc: Jordan Justen
Rafael Antognolli (18):
anv
h the address. But if they are in the higher 32 bits, they get
discarded.
On Gen10 we have fields that share space with the higher 16 bits of the
address too. This commit makes sure those fields don't get discarded.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
---
src/in
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.
v4: Remove redundant #if clause for GEN <= 10 (Jason)
Signed-off-by: Rafael Antognolli
Reviewed-by: Jason Ekstrand
---
src/intel/blorp/blorp_genX_exec.h | 13 ++---
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
v4: Use the clear color offset from the clear_color_bo, when available.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965
We only need to copy the clear color from the state buffer to the
inlined surface state when doing a resolve.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/src/intel/blorp
The lower bits seem to have extra fields in every platform but gen8
(even though we don't use them in gen9). So just go ahead and avoid
using them for the address.
v4: Use Jason's suggestion for comment explaining the change.
Signed-off-by: Rafael Antognolli
Reviewed-by: Jaso
Instead of updating the clear color in anv before a resolve, just let
blorp handle that for us during fast clears.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_blorp.c | 69 +++---
src/intel/vulkan/anv_private.h | 6 ++--
src/intel/vulkan
Store the default clear address for HiZ fast clears on a global bo, and
point to it when needed.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_device.c | 19 +++
src/intel/vulkan/anv_image.c | 10 +++---
src/intel/vulkan/anv_private.h | 1 +
3 files changed
helper to extract clear color from attachment (Jason)
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_image.c | 17 +
src/intel/vulkan/anv_private.h | 5
src/intel/vulkan/genX_cmd_buffer.c | 52 +++---
3 files changed, 70
everything in blorp, hopefully removing a lot of code
duplication. It also allows us to have a similar behavior on gen < 9 and
gen >= 10.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 48 +++
1 file changed, 48 insertions(+)
diff
struct
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 16
2 files changed, 32 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri
t;Clear Color Address"
to "Clear Value Address" and use it for both color and depth. Do the
same for the high bits.
TODO: add support for multiple addresses at the same position in the
xml.
v2: Combine high and low order bits into a single address field.
Signed-off-by: Rafael Antognoll
Add an extra BO to store clear color when we receive the aux buffer from
the window system. Since we have no control over the aux buffer size in
this case, we need the new BO to store only the clear color.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18
In a follow up patch, we make use of clear_color_bo, which is in
mt->mcs_buf or mt->hiz_buf. To avoid duplicating more code that does the
same thing on both aux buffers, just use aux_buf already.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.
available.
- let core blorp update the clear color, but also update it when we
skip a fast clear depth.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 11 +++
src/mesa/drivers/dri/i965/brw_clear.c | 22 ++
2 files changed, 33 insertions
d-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h| 4
src/intel/isl/isl.c | 2 +-
src/intel/isl/isl.h | 7 +++
src/intel/isl/isl_surface_state.c| 21 +++--
src/
Tested-by: Rafael Antognolli
On Fri, Mar 09, 2018 at 04:29:41PM -0800, Scott D Phillips wrote:
> Different registers are used for execlist submission in gen11, so
> also watch those. This code only watches element zero of the
> submit queue, which is all aubdump currently writes.
>
Make sure we don't emit 64 bit types if the hardware doesn't support
them.
Signed-off-by: Rafael Antognolli
Suggested-by: Kenneth Graunke
---
src/intel/compiler/brw_reg_type.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/compiler/brw_reg_type.c
b/src/inte
On Wed, Mar 14, 2018 at 05:26:08PM -0700, Jordan Justen wrote:
> What about a subject like this?
>
> i965/miptree: Add new clear color BO for winsys aux buffers
It's definitely better. I'll update it.
> On 2018-03-08 08:49:03, Rafael Antognolli wrote:
> > Add an e
On Thu, Mar 15, 2018 at 12:20:19AM -0700, Jordan Justen wrote:
> On 2018-03-08 08:49:07, Rafael Antognolli wrote:
> > Extract the code from color_attachment_compute_aux_usage, so we can
> > later reuse it to update the clear color state buffer.
> >
> > Signe
On Thu, Mar 15, 2018 at 04:49:07PM +, Lionel Landwerlin wrote:
> A few trivial compiler warnings we can get rid of :)
Trivial review too :)
Reviewed-by: Rafael Antognolli
> Cheers,
>
> Lionel Landwerlin (3):
> anv: silence unused function warning on gen11
> i9
Set bit when initializing a device.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/genX_state.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index c6e54046910..3b5ac10b4cd 100644
--- a/src/intel
Set bit when initializing context.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 2 ++
src/mesa/drivers/dri/i965/brw_defines.h | 5 +
src/mesa/drivers/dri/i965/brw_state.h| 3 ++-
src/mesa/drivers/dri/i965/brw_state_upload.c | 25
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen10.xml | 8
src/intel/genxml/gen11.xml | 8
src/intel/genxml/gen9.xml | 8
3 files changed, 24 insertions(+)
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 2d36957c2a5..f6773074a61
ignore blorp. The only primitive it emits is
3DPRIM_RECTLIST, and since it's not listed in the workarounds, we can
safely leave preemption enabled when it happens. Or it will be disabled
by a previous 3DPRIMITIVE, which should be fine too.
Signed-off-by: Rafael Antognolli
Cc: Kenneth Gr
the workarounds for anv too in the future, but I
thought I could send these now while I figure out how to do that in
vulkan.
Cc: Ben Widawsky
Rafael Antognolli (4):
intel/genxml: Add register for object preemption.
anv/gen10: Enable object level preemption.
i965/gen10+: Enable object level
n we get the write to the control
register, decode the context.
It makes sense, but maybe in the future it might be better to split this
into two separate functions, one for elsp and another one for elsq.
Either way, for now this is:
Reviewed-by: Rafael Antognolli
> - uint8_t *pphwsp
ot;)
Oh, it makes sense to fail, but I don't know why I didn't see any error
on CI when I submitted this. Is it part of some test not covered by
percheckin?
Either way, both patches are
Reviewed-by: Rafael Antognolli
> ---
> src/intel/Makefile.compiler.am | 1 +
&g
On Wed, Jan 24, 2018 at 11:29:12AM +0200, Pohjolainen, Topi wrote:
> On Fri, Jan 19, 2018 at 11:54:35AM -0800, Rafael Antognolli wrote:
> > Second version of this series, with (hopefully) full support for this in
> > Vulkan.
>
> I started reading this but realized quickly th
The GPU hang caused by push constants is apparently fixed, so let's
enable them again.
Signed-off-by: Rafael Antognolli
Cc: "18.0"
---
src/intel/compiler/brw_fs.cpp | 9 -
1 file changed, 9 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/b
Similar to the GL driver, ignore 3DSTATE_CONSTANT_* packets when doing a
context restore.
Signed-off-by: Rafael Antognolli
Cc: Jason Ekstrand
Cc: "18.0"
---
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/genX_cmd_buffer.c | 47 +
GPU hangs on CNL. The (partial) solution to this
problem so far was to entirely disable push constants on this platform.
Signed-off-by: Rafael Antognolli
Cc: Kenneth Graunke
Cc: "18.0"
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 49 +++
src/m
On Wed, Jan 24, 2018 at 05:08:54PM -0800, Jason Ekstrand wrote:
> On Wed, Jan 24, 2018 at 4:33 PM, Rafael Antognolli
> > wrote:
>
> Similar to the GL driver, ignore 3DSTATE_CONSTANT_* packets when doing a
> context restore.
>
> Signed-off-by: Rafael Ant
Fixes: ca19ee33d7d39cb89d948b1c983763065975ce5b
Signed-off-by: Rafael Antognolli
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers
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