Reviewed-by: Rafael Antognolli
On Thu, May 04, 2017 at 08:13:05AM -0700, Kenneth Graunke wrote:
> We can use a simple shift equation rather than a switch statement.
> ---
> src/mesa/main/varray.c | 12 ++--
> 1 file changed, 2 insertions(+), 10 deletions(-)
>
> dif
brw_state.h is a better place to keep them, instead of brw_context.h.
Signed-off-by: Rafael Antognolli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h | 42 -
src/mesa/drivers/dri/i965/brw_state.h | 42
On Wed, May 03, 2017 at 11:36:29PM -0700, Kenneth Graunke wrote:
> On Wednesday, May 3, 2017 7:52:01 PM PDT Pohjolainen, Topi wrote:
> > On Wed, May 03, 2017 at 05:11:45PM -0700, Rafael Antognolli wrote:
> > > On Wed, May 03, 2017 at 08:28:24PM +0300, Pohjolainen, Topi wrote:
&
On Thu, May 04, 2017 at 11:19:24AM +0300, Pohjolainen, Topi wrote:
> On Mon, May 01, 2017 at 06:43:23PM -0700, Rafael Antognolli wrote:
> > Some code that was placed in brw_draw_upload.c and exported to be used
> > by gen8+ was also moved to genX_state_upload, and the respective
On Fri, May 05, 2017 at 08:38:53AM +0300, Pohjolainen, Topi wrote:
> On Thu, May 04, 2017 at 12:16:53PM -0700, Rafael Antognolli wrote:
> > On Thu, May 04, 2017 at 11:19:24AM +0300, Pohjolainen, Topi wrote:
> > > On Mon, May 01, 2017 at 06:43:23PM -0700, Rafael Antognolli wrote:
On Fri, May 05, 2017 at 11:47:09AM +0100, Emil Velikov wrote:
> From: Emil Velikov
>
> Signed-off-by: Emil Velikov
> ---
> src/mesa/drivers/dri/i965/brw_state.h | 1 +
> src/mesa/drivers/dri/i965/genX_blorp_exec.c | 6 +
> src/mesa/drivers/dri/i965/genX_state_upload.c | 32
> ++
Several issues were caught on review after the original patch landed.
This commit fixes them.
Signed-off-by: Rafael Antognolli
Cc: "Pohjolainen, Topi"
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 49 +++
1 file changed, 20 insertions(+), 29 deletion
While moving depth stencil state to use genxml, this one was left
behind.
Signed-off-by: Rafael Antognolli
Cc: "Pohjolainen, Topi"
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/genX_stat
There's no &sb->_vg_ptr in that case.
Signed-off-by: Rafael Antognolli
Cc: Jason Ekstrand
---
src/intel/vulkan/anv_allocator.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index e2f2dea..6d04b63 100644
---
t;
> Then rename brw_get_line_width_float() to the shorter name.
Hmm... I should have looked for other users of this function before creating
the _float() version.
Reviewed-by: Rafael Antognolli
> ---
> src/mesa/drivers/dri/i965/brw_util.h | 10 +-
> src/mesa/drivers/dri/i965/genX_st
> section of code - usually a single function/atom, or sometimes a group
> of related functions. It should make the code easier to work on.
Reviewed-by: Rafael Antognolli
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 41
> +--
> 1 file changed,
With this last state ported, we can get rid of gen8_draw_upload.c.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 53 ---
src
Also make the brw_get_index_type() function not shift its return, since that
is genxml's job now.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_context.h | 6 ++--
src/mesa/drivers/dri/i965/brw_draw_upload.c | 39 -
src/mesa/drivers/dri
Use an alias for this field on 3DSTATE_INDEX_BUFFER on gen6+, so we can set
the same value as the defines.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 1 +
src/intel/genxml/gen7.xml | 1 +
src/intel/genxml/gen75.xml | 1 +
src/intel/genxml/gen8.xml | 1 +
src/intel
Emit the respective commands using genxml code.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/gen7_cs_state.c | 162 --
src/mesa/drivers/dri/i965/genX_state_upload.c | 146
Several issues were caught on review after the original patch landed.
This commit fixes them.
v2:
- Fix padding (Topi)
- Remove .DestinationElementOffset change from this patch (Topi)
Signed-off-by: Rafael Antognolli
Reviewed-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965
On Wed, May 10, 2017 at 11:36:46AM +0300, Pohjolainen, Topi wrote:
> On Tue, May 09, 2017 at 05:12:09PM -0700, Rafael Antognolli wrote:
> > Use an alias for this field on 3DSTATE_INDEX_BUFFER on gen6+, so we can set
> > the same value as the defines.
> >
> > Signe
Reviewed-by: Rafael Antognolli
On Wed, May 10, 2017 at 12:41:38PM -0700, Kenneth Graunke wrote:
> This whole code is surrounded in #if GEN_GEN >= 6, and this code only
> applies on Sandybridge. So, use GEN_GEN == 6 to reduce the delta in
> the next patch, when we add Ge
ext *brw)
> {
> + UNUSED struct gl_context *ctx = &brw->ctx;
> const struct gen_device_info *devinfo = &brw->screen->devinfo;
> - const struct brw_stage_state *stage_state = &brw->vs.base;
> + struct brw_stage_state *stage_state = &brw->
Ugh, and I also forgot: you can remove brw_vs_unit from brw_state.h too.
On Thu, May 11, 2017 at 09:54:13AM -0700, Rafael Antognolli wrote:
> On Wed, May 10, 2017 at 12:41:39PM -0700, Kenneth Graunke wrote:
> > It's actually not that much code.
> > ---
> >
On Thu, Nov 09, 2017 at 12:59:12AM -0800, Jordan Justen wrote:
> Reviewed-by: Jordan Justen
It's also
Tested-by: Rafael Antognolli
> On 2017-11-08 10:56:00, Kenneth Graunke wrote:
> > Similar to what we did for pixel shader threads - see gen_device_info.c.
> >
> &
On Thu, Nov 09, 2017 at 01:50:29PM -0800, Kenneth Graunke wrote:
> On Thursday, November 9, 2017 11:22:34 AM PST Rafael Antognolli wrote:
> > On Thu, Nov 09, 2017 at 12:59:12AM -0800, Jordan Justen wrote:
> > > Reviewed-by: Jordan Justen
> >
> > It's also
&g
On Fri, Nov 10, 2017 at 10:46:03AM +, Julien Isorce wrote:
> Thx for the suggestions.
>
> Anyone familiar with _mesa_get_format_block_size and _mesa_get_format_bytes
> wants to review this patch ?
>
> On 9 November 2017 at 17:10, Eric Engestrom wrote:
>
> On Thursday, 2017-11-09 17:03:
Since it's anv, I would like to hear from Jason or Nanley too. But it
does seem to implement the workaround correctly, like we do in i965, so
you have my
Reviewed-by: Rafael Antognolli
On Thu, Nov 09, 2017 at 11:14:42AM -0800, Anuj Phogat wrote:
> We already have this workaround i
On Thu, Nov 09, 2017 at 11:14:43AM -0800, Anuj Phogat wrote:
> On CNL this bit has been moved to CACHE_MODE_SS register.
> We already have this enabled in OpenGL driver.
> See Mesa commit 6c681b4cc1
>
> Signed-off-by: Anuj Phogat
> Cc: Nanley Chery
> Cc: Rafael Antognoll
It seems I missed that one when reviewing before, thank you.
Reviewed-by: Rafael Antognolli
On Fri, Nov 10, 2017 at 01:39:22PM -0800, Jason Ekstrand wrote:
> Found by inspection
>
> Fixes: d3d0fe4572f62474b86ef3a68405046c68b54062
> Cc: Anuj Phogat
> ---
> src/mes
Reviewed-by: Rafael Antognolli
On Tue, Nov 14, 2017 at 03:24:36PM -0800, Kenneth Graunke wrote:
> ...and provide a better citation for the existing one.
>
> v2:
> - Apply the workaround to Gen8 too, as intended (caught by Topi).
> - Restructure to add bits instead of an extra fl
Xorg (and possibly other things) depend on this variable to find the
path to DRI drivers.
Signed-off-by: Rafael Antognolli
Cc: Dylan Baker
---
src/mesa/drivers/dri/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/meson.build b/src/mesa/drivers/dri
The bspec describes:
"WA: Clear tdr register before send EOT in all non-PS shader kernels
mov(8) tdr0:ud 0x0:ud {NoMask}"
Signed-off-by: Rafael Antognolli
---
src/intel/compiler/brw_fs_generator.cpp | 7 +++
src/intel/compiler/brw_reg.h| 6 ++
2 files c
On CNL, we see multiple multisample failures on piglit tests. By
emitting this extra state, though not documented in the bspec, those
failures seem to go away.
This workaround could be removed if we ever find out a better solution,
but it should be good enough for now.
Signed-off-by: Rafael
It looks like I forgot to prefix the subject with "intel/compiler:".
Fixed locally.
On Thu, Nov 30, 2017 at 04:42:48PM -0800, Rafael Antognolli wrote:
> The bspec describes:
>
>"WA: Clear tdr register before send EOT in all non-PS shader kernels
>
>
I believe the workaround describes that the MI_LOAD_REGISTER_IMM should
come right after the 3DSTATE_SAMPLE_PATTERN.
Signed-off-by: Rafael Antognolli
Cc: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen8_multisample_state.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
On Fri, Dec 01, 2017 at 10:33:26AM +0200, Pohjolainen, Topi wrote:
> On Thu, Nov 30, 2017 at 04:50:19PM -0800, Rafael Antognolli wrote:
> > It looks like I forgot to prefix the subject with "intel/compiler:".
> > Fixed locally.
> >
> > On Thu, Nov 30, 2017 a
This series is
Reviewed-by: Rafael Antognolli
On Mon, Dec 04, 2017 at 04:21:26PM +, Lionel Landwerlin wrote:
> Hi all,
>
> We've had some timestamp related issues on Gen10. Those are mostly
> related to the fact that the frequency of the timestamps is variable
> depen
We still have gpu hangs on Cannonlake when using push constants, so
disable them for now until we have a proper fix for these hangs.
Signed-off-by: Rafael Antognolli
---
src/intel/compiler/brw_fs.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b
Indeed the other two commits are related to the no_error path, but I
think at least this one should be applied. So it is:
Reviewed-by: Rafael Antognolli
On Wed, Jun 14, 2017 at 07:33:12PM +0300, Plamena Manolova wrote:
> In blit_framebuffer we're already doing a NULL
> pointer check
Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_cc.c| 174 --
src/mesa/drivers/dri/i965/brw_state.h | 1
This is a bitmask, so it can't be a boolean. Also rename it so it matches
gen6+.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/
Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 182
Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen5.xml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
index 65479d2..4651
code that handles it.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/mesa/drivers/dri/i965/gen4_blorp_exec.h | 2 +-
4 files changed, 4 insertions(
ction.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 2 -
src/mesa/drivers/dri/i965/gen6_gs_state.c | 56 ---
src/mesa/drivers/dri/i965/genX_state_upload.c | 17 +++-
4 files ch
apply
to lower gens.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index
These fields are set by brw_clip_unit, so we need them when converting to
genxml.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen45.xml | 1 +
src/intel/genxml/gen5.xml | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml
index
Just because it's not set doesn't mean that it doesn't exist. And since the
field is there on newer gens, having it on gen5 simplifies the code when
porting gen5 and lower.
Also add missing value to API Mode on CLIP_STATE on gen4.
Signed-off-by: Rafael Antognolli
---
src/intel/
On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register
Count, but we can make the code that handles this on multiple gens simpler if
we add an index 0 to it too.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 4 ++--
src/intel/genxml/gen45
In newer gens, this field has a prefix and the non-I-745 mode is called
"Alternate", instead of simply "Alt".
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen6.xml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/genxml/gen6.xm
The code doesn't get exactly a lot simpler but at least it is in a
single place, and we delete more than we add.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_clip_state.c| 147 ---
src
"Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's
called on newer gens.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml
Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c,
together with brw_gs_unit_state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_gs_state.c | 101 --
src/mesa/drivers/dri/i965
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_cc.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa/drivers/dr
From: Kenneth Graunke
Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and
BLEND_STATE together into a single COLOR_CALC_STATE structure.
By making a helper function, we'll be able to reuse it when filling
out Gen4-5 COLOR_CALC_STATE without replicating any actual logic.
We use gene
It's a very simple conversion, and it allows us to delete brw_cc.c.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_cc.c| 62 ---
src/mesa/drivers/dri/i965/genX_state_upload.c
The code doesn't get exactly a lot simpler but at least it is in a single
place, and we delete more than we add.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri
On Sat, Jun 17, 2017 at 10:38:26AM -0700, Kenneth Graunke wrote:
> On Friday, June 16, 2017 4:31:24 PM PDT Rafael Antognolli wrote:
> > gen6+ uses _mesa_base_format_has_channel() to check for the alpha
> > channel, while gen4-5 use ctx->DrawBuffer->Visua
On Sat, Jun 17, 2017 at 10:32:44AM -0700, Kenneth Graunke wrote:
> On Friday, June 16, 2017 4:31:23 PM PDT Rafael Antognolli wrote:
> > Add a helper function to reuse code that fills blend entry related
> > state, and make genX(upload_blend_state) use it. This function can later
On Sat, Jun 17, 2017 at 11:31:51AM -0700, Kenneth Graunke wrote:
> On Friday, June 16, 2017 4:31:25 PM PDT Rafael Antognolli wrote:
> > Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
> > color calc struct, and then manually update the rest.
> >
>
On Mon, Jun 19, 2017 at 09:46:30AM -0700, Kristian Høgsberg wrote:
> On Fri, Jun 16, 2017 at 4:31 PM, Rafael Antognolli
> wrote:
> > The code doesn't get exactly a lot simpler but at least it is in a single
> > place, and we delete more than we add.
>
> Another good
This makes the code more consistent accross generations.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_cc.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa
It's a very simple conversion, and it allows us to delete brw_cc.c.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_cc.c| 62 ---
src/mesa/drivers/dri
Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c,
together with brw_gs_unit_state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_gs_state.c | 101 --
src/mesa/drivers/dri/i965
apply
to lower gens.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/
Add a helper function to reuse code that fills blend entry related
state, and make genX(upload_blend_state) use it. This function can later
be used by gen4-5 color calc state to set the blend related bits.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri
These were originally used to submit state changes using manual packing
of instructions, but we are now using genxml for that. So it should be
safe to just remove them.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_defines.h | 729 +---
1 file
e use generation-defined typedef to handle the polymorphism.
Reviewed-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 113 +++---
1 file changed, 65 insertions(+), 48 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/dr
ction.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 2 -
src/mesa/drivers/dri/i965/gen6_gs_state.c | 56 ---
src/mesa/drivers/dri/i965/genX_state_upl
to me, this change also seems to fix fbo-blending-formats piglit test on
gen4.
Signed-off-by: Rafael Antognolli
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_cc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa/d
ructs. Now we're down to
just GENXML and some manual packing. (Khristian)
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_state.h | 1 -
src/mesa/drivers/dri/i965/brw_structs.h | 121
Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the
color calc struct, and then manually update the rest.
v2:
- Always check for depth_irb (Ken)
- Always set Backface Stencil Ref (Ken)
- Always set alpha reference value (Ken)
Signed-off-by: Rafael Antognolli
The code doesn't get exactly a lot simpler but at least it is in a
single place, and we delete more than we add.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
src/mesa/drivers/dri/i965/brw_clip_state.c| 147 ---
src
Reviewed-by: Rafael Antognolli
On Tue, Jun 13, 2017 at 11:28:20AM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen10.xml | 69
> +++---
> 1 file changed, 65 insertions(+), 4 deletions(-)
>
> d
There are a few fields missing but they don't seem to be used anyway, so:
Reviewed-by: Rafael Antognolli
On Tue, Jun 13, 2017 at 11:28:21AM -0700, Anuj Phogat wrote:
> Signed-off-by: Anuj Phogat
> ---
> src/intel/genxml/gen10.xml | 115
> +
ot;/>
> + type="uint"/>
> + type="bool"/>
> + type="bool"/>
> + type="bool"/>
> + type="bool"/>
> +
Bit 14 and 1 changed name. Bits 8-6, and 4 seem to have been removed. And I
believe the resp
From: Eero Tamminen
Commit f8d69beed49c64f883bb8ffb28d4960306baf575 moving sampler
handling to genxml messed up change done by commit
6a7c5257cac23cd9767aa4bc8fdab68925b11157.
This broke rendering in SynMark CSDof and TexFilterAniso tests.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=
t;Clear Color Address"
to "Clear Value Address Low" and use it for both color and depth. Do the
same for the high bits.
TODO: add support for multiple addresses at the same position in the
xml.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen10.xml | 10 ++
1 fi
gen10 can emit the clear color by setting it on a buffer somewhere, and
then adding only the address to the surface state.
This commit add support for that on isl_surf_fill_state, and if that is
requested, skip setting the clear value itself.
Signed-off-by: Rafael Antognolli
---
src/intel/isl
On Gen10, whenever the fast clear color changes, update it on the clear
color entry buffer. This allow us to use it directly when emitting the
surface state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 26 ++
1 file changed, 26 insertions
Similarly to vulkan where we store the clear value in the aux surface,
we can do the same in GL.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel/bl
This warning showed up after aux_bo started being used inside
if (use_clear_address) {...
But use_clear_address depends on aux_surf being not null, in which case
aux_bo would also be set. Make the compiler happy anyway.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16
1 file changed, 16 insertions
On Gen10+, if we use the clear state address field in the surface state
instead of the clear color directly, there's a restriction that the
address must point to the lower part of a 64 byte cache-line.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_private.h | 12 +++-
1
We still have gpu hangs on Cannonlake when using push constants, so
disable them for now until we have a proper fix for these hangs.
v2: Add warning message when creating context too.
Signed-off-by: Rafael Antognolli
Cc: Ben Widawsky
Cc: Kenneth Graunke
---
src/intel/compiler/brw_fs.cpp
I can confirm this fixes the 2000+ failures.
Tested-by: Rafael Antognolli
On Fri, Dec 22, 2017 at 01:54:08PM -0800, Anuj Phogat wrote:
> This reverts commit 9cd60fce9c22737000a8f8dc711141f8a523fe75.
> Above commit caused 2000+ piglit tests to assert fail. Disabling
> the align1 mode
nable/disable kind of boolean. In other similar places we used "uint"
instead of "bool" to represent that, specially since you are assigning
value names to it. For instance, Floating Point Mode is like that, but
there are other examples. May
On Mon, Jan 08, 2018 at 03:14:54PM -0800, Nanley Chery wrote:
> On Fri, Dec 15, 2017 at 02:53:32PM -0800, Rafael Antognolli wrote:
> > Similarly to vulkan where we store the clear value in the aux surface,
> > we can do the same in GL.
> >
> > Signed-off-by: Rafael A
On Mon, Jan 08, 2018 at 04:03:47PM -0800, Jason Ekstrand wrote:
> On Mon, Jan 8, 2018 at 3:00 PM, Nanley Chery wrote:
>
> On Fri, Dec 15, 2017 at 02:53:30PM -0800, Rafael Antognolli wrote:
> > On Gen10+, if we use the clear state address field in the surface state
>
On Mon, Jan 08, 2018 at 04:06:53PM -0800, Jason Ekstrand wrote:
> On Fri, Dec 15, 2017 at 2:53 PM, Rafael Antognolli
> > wrote:
>
> On gen10+, if surface->clear_color_addr is present, use it directly
> intead of copying it to the surface state.
>
> Signe
The lower bits seem to have extra fields in every platform but gen8
(even though we don't use them in gen9). So just go ahead and avoid
using them for the address.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_image.c | 30 +-
1 file change
Second version of this series, with (hopefully) full support for this in
Vulkan.
Rafael Antognolli (12):
anv/image: Do not override lower bits of dword.
genxml: Preserve fields that share dword space with addresses.
intel/genxml: Use a single field for clear color address on gen10.
intel
Similarly to vulkan where we store the clear value in the aux surface,
we can do the same in GL.
v2: Remove unneeded extra function.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/mesa
.
Signed-off-by: Rafael Antognolli
---
src/intel/isl/isl.h | 9 +
src/intel/isl/isl_surface_state.c | 18 ++
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index e3acb0ec280..c6e1fee27c1 100644
--- a
h the address. But if they are in the higher 32 bits, they get
discarded.
On Gen10 we have fields that share space with the higher 16 bits of the
address too. This commit makes sure those fields don't get discarded.
Signed-off-by: Rafael Antognolli
---
src/intel/genxml/gen_pack_header.py | 9 ++
On Gen10, whenever the fast clear color changes, update it on the clear
color entry buffer. This allow us to use it directly when emitting the
surface state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_blorp.c | 26 ++
1 file changed, 26 insertions
t;Clear Color Address"
to "Clear Value Address" and use it for both color and depth. Do the
same for the high bits.
TODO: add support for multiple addresses at the same position in the
xml.
v2: Combine high and low order bits into a single address field.
Signed-off-by: Rafael Antogno
On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
Signed-off-by: Rafael Antognolli
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16
1 file changed, 16 insertions
OD is present. The clear state address is at the beginning of the
buffer, so it will be aligned as well.
v2: Trying to improve commit message.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_private.h | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/intel/v
On gen10+, if surface->clear_color_addr is present, use it directly
intead of copying it to the surface state.
Signed-off-by: Rafael Antognolli
---
src/intel/blorp/blorp_genX_exec.h | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/intel/bl
This warning showed up after aux_bo started being used inside
if (use_clear_address) {...
But use_clear_address depends on aux_surf being not null, in which case
aux_bo would also be set. Make the compiler happy anyway.
Signed-off-by: Rafael Antognolli
Reviewed-by: Nanley Chery
---
src/mesa
On Gen10+, instead of copying the clear color from the state buffer to
the surface state, just use the address of the state buffer in the
surface state directly. This way we can avoid the copy from state buffer
to surface state.
Signed-off-by: Rafael Antognolli
---
src/intel/vulkan/anv_image.c
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