On Gen10, when emitting the surface state, use the value stored in the
clear color entry buffer by using a clear color address in the surface
state.
Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 38af6bc0dea..98323976622 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -182,6 +182,10 @@ brw_emit_surface_state(struct brw_context *brw,
brw->isl_dev.ss.align,
surf_offset);
+ bool use_clear_address = devinfo->gen >= 10 && aux_surf;
+ uint32_t clear_offset =
+ use_clear_address ? aux_offset + aux_surf->size : 0;
+
isl_surf_fill_state(&brw->isl_dev, state, .surf = &mt->surf, .view = &view,
.address = brw_state_reloc(&brw->batch,
*surf_offset +
brw->isl_dev.ss.addr_offset,
@@ -190,6 +194,8 @@ brw_emit_surface_state(struct brw_context *brw,
.aux_address = aux_offset,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.clear_color = clear_color,
+ .use_clear_address = use_clear_address,
+ .clear_address = clear_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
if (aux_surf) {
/* On gen7 and prior, the upper 20 bits of surface state DWORD 6 are the
@@ -208,6 +214,16 @@ brw_emit_surface_state(struct brw_context *brw,
aux_bo, *aux_addr,
reloc_flags);
}
+
+ if (use_clear_address) {
+ /* Make sure the offset is aligned with a cacheline. */
+ assert((clear_offset & 0x3f) == 0);
+ uint32_t *clear_address = state + brw->isl_dev.ss.clear_value_offset;
+ *clear_address = brw_state_reloc(&brw->batch,
+ *surf_offset +
+ brw->isl_dev.ss.clear_value_offset,
+ aux_bo, *clear_address, reloc_flags);
+ }
}
static uint32_t
--
2.14.3
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