-VK.api.copy_and_blit.resolve_image.with_regions_4_bit
dEQP-VK.api.copy_and_blit.resolve_image.with_regions_8_bit
Tested on IVB/HSW
Signed-off-by: Lionel Landwerlin
Cc: anuj.pho...@gmail.com
---
src/intel/vulkan/gen7_pipeline.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/intel/vulkan
Hi,
This updates a previous patch, based on the review feedback from Anuj.
Thanks a lot for your time!
Lionel
Lionel Landwerlin (2):
anv: gen7: rename rasterization state variable
anv: gen7/75: enable multisampling
src/intel/vulkan/gen7_pipeline.c | 39
-VK.api.copy_and_blit.resolve_image.with_regions_4_bit
dEQP-VK.api.copy_and_blit.resolve_image.with_regions_8_bit
Tested on IVB/HSW
v2: Check pMultisampleState is not NULL
Signed-off-by: Lionel Landwerlin
Cc: Anuj Phogat
---
src/intel/vulkan/gen7_pipeline.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff
-VK.api.copy_and_blit.resolve_image.with_regions_4_bit
dEQP-VK.api.copy_and_blit.resolve_image.with_regions_8_bit
Tested on IVB/HSW
v2: Check pMultisampleState is not NULL
v3: Drop rasterization state rename (Anuj)
Fix value of MultisampleRasterizationMode in 3DSTATE_SF
Signed-off-by: Lionel Landwerlin
Cc: Anuj Phogat
---
src/intel
For the series :
Reviewed-by: Lionel Landwerlin
On 11/01/2019 21:05, Jason Ekstrand wrote:
A long time in a galaxy far far away, there was a GLSLang bug with how
it handled samplers passed in as function parameters. (The bug can be
found here: https://github.com/KhronosGroup/glslang/issues
On 12/01/2019 08:04, Jason Ekstrand wrote:
Even though no one's been brave enough to ever use this pass, I like to
keep it functionally working.
Reviewed-by: Lionel Landwerlin
---
src/compiler/nir/nir_opt_gcm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/compile
On 12/01/2019 03:45, Jason Ekstrand wrote:
Instead of emitting all of the conditions for the cases of a switch
statement up-front, emit them on-the-fly as we emit the code for each
case. The original justification for this was that we were going to
have to build a default case anyway which would
On 12/01/2019 15:29, Jason Ekstrand wrote:
On January 12, 2019 03:06:07 Lionel Landwerlin
wrote:
On 12/01/2019 03:45, Jason Ekstrand wrote:
Instead of emitting all of the conditions for the cases of a switch
statement up-front, emit them on-the-fly as we emit the code for each
case. The
On 12/01/2019 18:24, Ilia Mirkin wrote:
On Sat, Jan 12, 2019 at 9:40 AM Gert Wollny wrote:
I will not push it with
the strong NAK you gave, Ilia. To me consensus means that all who
contribute significantly to the project (like you certainly do) agree
or abstain, but don't object.
A single acto
makes AYUV buffers
display as expected.
CC: Lionel Landwerlin
CC: Tapani Palli
Signed-off-by: Vivek Kasireddy
---
src/compiler/nir/nir_lower_tex.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c
index a6
On 16/01/2019 01:31, Matt Turner wrote:
On Mon, Oct 29, 2018 at 11:16 AM Lionel Landwerlin
wrote:
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_sanitize_gpu.in | 55 ++-
1 file changed, 54 insertions(+), 1 deletion(-)
diff --git a/src/intel/tools
- I'm pretty happy with the discussion on a particular point/location of
a change.
A lot more readable than a long chain of email.
- Having issues with the comments not always showing up on a particular
commit of an MR (but it looks like gitlab is aware of that issue)
- The Rb/Ab tags were
On 16/01/2019 14:01, Daniel Stone wrote:
Hi,
On Wed, 16 Jan 2019 at 13:01, Lionel Landwerlin
wrote:
- It seems we only get notifications when adding to an MR, I could like to
subscribe to particular tags
If you go to https://gitlab.freedesktop.org/mesa/mesa/labels/ then you
can subscribe to
Sorry, for replying so late, going through my unread emails :(
We already have functions for doing this :
brw_load_register_reg
brw_load_register_imm32/64
brw_load_register_mem
Why not use those?
-
Lionel
On 13/11/2018 00:05, Jordan Justen wrote:
Signed-off-by: Jordan Justen
---
src/mesa/
Put a few nits below, but otherwise looks good.
-
Lionel
On 13/11/2018 00:05, Jordan Justen wrote:
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_compute.c | 131 +-
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/genX_
Looking at the change the binding table emission, I think the image++
has been moved such that it doesn't produce the same tables anymore.
Trying this change on CI :
https://github.com/djdeath/mesa/commit/a6b8eaf1325389d94d1d8a5b3bb952a362125eb2
On 17/01/2019 18:19, Clayton Craft wrote:
Quotin
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/132
2 change in this MR :
* add some documentation to clarify how we choose pipeline flushes
invalidations
* narrow the CS stall & RT flushes for the query copies to track
only operations that write a destination buffer
For the
Reviewed-by: Lionel Landwerlin
On 18/01/2019 16:24, Jason Ekstrand wrote:
I like to keep things in good order so that you can find them.
---
src/intel/vulkan/anv_extensions.py | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/intel/vulkan/anv_extensions.py
Doesn't save us a great deal of lines but at least they get decoded in
aubinators.
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml | 2 ++
src/intel/genxml/gen11.xml | 2 ++
src/intel/genxml/gen7.xml | 2 ++
src/intel/genxml/gen75.xml | 2 ++
Thanks, pushed to master.
On 18/01/2019 18:09, Rafael Antognolli wrote:
Reviewed-by: Rafael Antognolli
On Fri, Jan 18, 2019 at 05:01:58PM +, Lionel Landwerlin wrote:
Doesn't save us a great deal of lines but at least they get decoded in
aubinators.
Signed-off-by: Lionel Landw
Reviewed-by: Lionel Landwerlin
On 19/01/2019 19:04, Jason Ekstrand wrote:
---
src/intel/vulkan/anv_descriptor_set.c | 43 +++
1 file changed, 31 insertions(+), 12 deletions(-)
diff --git a/src/intel/vulkan/anv_descriptor_set.c
b/src/intel/vulkan
Signed-off-by: Lionel Landwerlin
---
src/vulkan/util/gen_enum_to_str.py | 8
1 file changed, 8 insertions(+)
diff --git a/src/vulkan/util/gen_enum_to_str.py
b/src/vulkan/util/gen_enum_to_str.py
index fb9ecd65c6d..06f74eb487c 100644
--- a/src/vulkan/util/gen_enum_to_str.py
+++ b/src
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/139
The start of a Vulkan layer to display some basic swapchain/draws/submit
information.
Looks like this : https://i.imgur.com/4zyIiVb.png
There is probably plenty of improvements that can be made to get closer
to the gallium HUD.
-Li
Thanks Caio, pushed to master.
On 22/01/2019 18:13, Caio Marcelo de Oliveira Filho wrote:
Reviewed-by: Caio Marcelo de Oliveira Filho
___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/TODO | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/intel/vulkan/TODO b/src/intel/vulkan/TODO
index b4da05de2b1..5b27cb2bd63 100644
--- a/src/intel/vulkan/TODO
+++ b/src/intel/vulkan/TODO
@@ -7,7 +7,4 @@ Missing Features
On 03/02/2019 16:04, Jason Ekstrand wrote:
They are effectively (&x)[0] or *&x which does nothing.
Reviewed-by: Lionel Landwerlin
---
src/compiler/nir/nir_deref.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/src/compiler/nir/nir_deref.c b/src/comp
Reviewed-by: Lionel Landwerlin
On 02/02/2019 08:07, Rodrigo Vivi wrote:
Align with kernel commits:
5e0f5a58b167 ("drm/i915/cfl: Adding another PCI Device ID.")
03ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
Cc: José Roberto de Souza
Cc: Kenne
ca3cf8e9aa ("drm/i915/icl: Adding few more device IDs for Ice Lake")
c0c46ca461f1 ("drm/i915/aml: Add new Amber Lake PCI ID")
c1c8f6fa731b ("drm/i915: Redefine some Whiskey Lake SKUs")
Cc: José Roberto de Souza
Signed-off-by: Rodrigo Vivi
Acked-by: Lionel Landwe
etely
different shader contents. This was causing the simulator to believe
that the ver
Thanks for finding this.
Reviewed-by: Lionel Landwerlin
tex pipeline was executing a fragment shader, which didn't
end up well.
---
src/intel/tools/intel_dump_gpu.c | 41 ++-
Fixes: 1f862e923cb "i965/fs: Optimize float conversions of byte/word..."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109601
Cc: Matt Turner
Tested-by: Lionel Landwerlin
With a new piglit test : https://patchwork.freedesktop.org/patch/286177/
---
src/intel/compiler/br
On 15/02/2019 14:43, Samuel Iglesias Gonsálvez wrote:
Signed-off-by: Samuel Iglesias Gonsálvez
Hey Samuel,
Thanks for this change. Would you mind changing the align_u32 in the
if() branch too?
It won't fix anything but that's just to be consistent.
With that :
Reviewed-
so we drop it.
Fixes CTS's CL#3500 test:
dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm
Signed-off-by: Samuel Iglesias Gonsálvez
That looks good to me :
Reviewed-by: Lionel Landwerlin
I'm doing a CI run just to convince myself, so if you ca
On 18/02/2019 15:08, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-18 15:06:15)
On 15/02/2019 14:43, Samuel Iglesias Gonsálvez wrote:
There are formats which bpp are not aligned to a power-of-two and
that can cause problems in the checks we do.
The cacheline size was a requirement
I did not find the PRM bit that says it must be 64b aligned, but I can
see that's what i915 checks.
Chris: If you have a pointer to it, I could add the quote.
Thanks!
Reviewed-by: Lionel Landwerlin
On 19/02/2019 12:06, Samuel Iglesias Gonsálvez wrote:
Signed-off-by: Samuel Igl
On 21/02/2019 13:30, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-02-21 12:57:09)
I did not find the PRM bit that says it must be 64b aligned, but I can
see that's what i915 checks.
Chris: If you have a pointer to it, I could add the quote.
In amongst the register specs,
PLANE_S
ght it was harder than that :)
Thanks!
Reviewed-by: Lionel Landwerlin
---
src/compiler/nir/nir_lower_clip_cull_distance_arrays.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_lower_clip_cull_distance_arrays.c
b/src/co
Pushed with the PRM quote, thanks!
On 22/02/2019 06:16, Samuel Iglesias Gonsálvez wrote:
Lionel, are you going to push it with this quote? I can add it
otherwise.
Sam
On Thu, 2019-02-21 at 13:41 +, Lionel Landwerlin wrote:
On 21/02/2019 13:30, Chris Wilson wrote:
Quoting Lionel
On 22/02/2019 15:51, Juan A. Suarez Romero wrote:
Fill out "Vertex Sub Pixel Precision Select" possible values.
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Lionel Landwerlin
---
src/intel/genxml/gen10.xml | 5 -
src/intel/genxml/gen11.xml | 5 -
src/intel/g
.
v2: explicitly set 3DSTATE_SF::VertexSubPixelPrecisionSelect (Jason)
v3: use _8Bit definition as value (Jason)
CC: Jason Ekstrand
CC: Kenneth Graunke
Signed-off-by: Juan A. Suarez Romero
Reviewed-by: Lionel Landwerlin
Cc: stable?
---
src/intel/vulkan/anv_device.c| 2 +-
src
+#if GEN_GEN >= 8
+ clip.VertexSubPixelPrecisionSelect = _8Bit;
+#endif
+
clip.ClipMode = CLIPMODE_NORMAL;
clip.TriangleStripListProvokingVertexSelect = 0;
Well spotted.
Reviewed-by: Lionel Landwerlin
___
mesa-dev mailing l
On 27/02/2019 06:55, Kenneth Graunke wrote:
On Tuesday, February 26, 2019 9:41:07 AM PST Christian Gmeiner wrote:
Push this format to the pipe driver unchanged.
Signed-off-by: Christian Gmeiner
---
include/GL/internal/dri_interface.h | 1 +
src/gallium/state_trackers/dri/dri2.c | 2 ++
2
Reviewed-by: Lionel Landwerlin
On 08/03/2019 15:52, Brian Paul wrote:
---
src/intel/common/gen_batch_decoder.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_batch_decoder.c
b/src/intel/common/gen_batch_decoder.c
index ff898d8..5cac983 100644
Reviewed-by: Lionel Landwerlin
Thanks!
On 08/03/2019 15:52, Brian Paul wrote:
---
src/intel/compiler/brw_vec4.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index fe36851..2e9de29 100644
--- a/src
On 11/03/2019 15:04, Eleni Maria Stea wrote:
Enabled the VK_EXT_sample_locations for Intel Gen >= 7.
---
src/intel/vulkan/anv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 9e4e03e
Reviewed-by: Lionel Landwerlin
On 12/03/2019 20:24, Jason Ekstrand wrote:
We've been fairly inconsistent about this so we should really choose
whether we're going to use VK_TRUE/FALSE or the C boolean values. The
Vulkan #defines are set to 1 and 0 respectively so it's the
There is merge request opened about this issue :
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/429
I think the deps need to be moved from src/vulkan/wsi/meson.build into
src/vulkan/meson.build as they apply to the overlay, utils & wsi.
Thanks,
-Lionel
On 16/03/2019 18:56, Tobias K
Reviewed-by: Lionel Landwerlin
On 19/03/2019 17:08, Jason Ekstrand wrote:
We initially set this lower because we didn't have SIMD32 support yet
but we've supported SIMD32 for quite some time now. We should bump it
up to the real limit.
---
src/intel/vulkan/anv_device.c | 2 +
Reviewed-by: Lionel Landwerlin
On 19/03/2019 19:15, Jason Ekstrand wrote:
---
src/compiler/nir/nir.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 67304af1d64..e4f012809e5 100644
--- a/src/compiler/nir/nir.h
+++ b
Hey there,
While enabling LibVA on the Ozone backend of ChromeOS (EGL/GLES2 without X), I
stumbled upon a crash.
This patch is a fix for that problem. It's pretty much a copy/paste of a
snippet already in EGL/wayland file.
Cheers,
-
Lionel
___
mesa-d
Signed-off-by: Lionel Landwerlin
---
src/egl/drivers/dri2/platform_drm.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/egl/drivers/dri2/platform_drm.c
b/src/egl/drivers/dri2/platform_drm.c
index 70bd7d4..f6b9c3a 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl
Signed-off-by: Lionel Landwerlin
---
src/egl/drivers/dri2/platform_drm.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/egl/drivers/dri2/platform_drm.c
b/src/egl/drivers/dri2/platform_drm.c
index 70bd7d4..f6b9c3a 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl
Hey there,
While enabling LibVA on ChromeOS with their Ozone backend (EGL/GLES2 without
X), I stumbled upon a crash.
Here is a simple patch to fix it. It's pretty much a copy/paste of a snippet
already in EGL/wayland.
Cheers,
-
Lionel
___
mesa-dev ma
This looks good, but I wonder whether we're missing a vk_errorf() in
anv_QueueSubmit() when we get an error from anv_cmd_buffer_execbuf().
In that case it looks like we won't abort.
On 18/05/17 21:51, Jason Ekstrand wrote:
This is mostly for running in our CI system to prevent dEQP from
continu
Reviewed-by: Lionel Landwerlin
On 18/05/17 22:09, Jason Ekstrand wrote:
We weren't wrapping this before because anv_cmd_buffer_execbuf may throw
a more meaningful error message. However, we do change the error code
into VK_ERROR_DEVICE_LOST, so we should print a new message.
---
src/
Cool, thanks!
Reviewed-by: Lionel Landwerlin
On 18/05/17 22:10, Jason Ekstrand wrote:
I just sent a patch to address that. Thanks!
On Thu, May 18, 2017 at 2:04 PM, Lionel Landwerlin
mailto:lionel.g.landwer...@intel.com>>
wrote:
This looks good, but I wonder whether we'r
This series is :
Reviewed-by: Lionel Landwerlin
Thanks for doing this.
Although you seem to have a multithreaded scenario in mind, this will
probably help single threaded stacks like Clutter/Cogl & Mesa all using
the same event queue.
-
Lionel
On 16/05/17 11:05, Daniel Stone w
We're already verified that 'window' wasn't NULL, I'm guess this
allocation error is about the newly created queue.
CID: 1409754
Signed-off-by: Lionel Landwerlin
---
src/egl/drivers/dri2/platform_wayland.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
Hi, (hopefully right list this time)
Mark kindly pointed me at some coverity issues in aubinator. Here are
some cleanups.
Cheers,
Lionel Landwerlin (3):
aubinator: fix double free
aubinator: be consistent on exit code
aubinator: report error on unknown device id
src/intel/tools
Free previously allocated filename outside the for loop.
CID: 1405014
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator_error_decode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools
We're using both exit(1) & exit(EXIT_FAILURE), settle for one, same
for success.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator_error_decode.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/
Since we're going to stop aubinator without a valid device id, better
report an error. This also silences a Coverity warning.
CID: 1405004
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/aubinator_error_decode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/
of times (count
field in genxml).
The more fancy case is when you have only a single group of unknown
size (count=0). In that case we keep on reading that group for as long
as we're within the DWordLength of that instruction.
Signed-off-by: Lionel Landwerlin
---
src/intel/commo
The kernel already uses that feature and it would be nice to have
aubinator be able to dump those.
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen4.xml | 10 ++--
src/intel/genxml/gen5.xml | 10 ++--
src/intel/genxml/gen6.xml | 10 ++--
src/intel
Here are a couple of commits I used to debug writing dozen of
registers to restore the NOA configs in the kernel.
Might be useful to somebody :)
Cheers,
Lionel Landwerlin (2):
intel: gen-decoder: rework how we handle groups
genxml/anv: enable MI_LOAD_REGISTER* to load more than 1 register
On 30/05/17 22:39, Rafael Antognolli wrote:
On Tue, May 30, 2017 at 08:59:06PM +0100, Lionel Landwerlin wrote:
The current way of handling groups doesn't seem to be able to handle
MI_LOAD_REGISTER_* with more than one register.
Hi Lionel, I don't think this is entirely true. I
Reviewed-by: Lionel Landwerlin
On 20/05/17 08:24, Kenneth Graunke wrote:
For example,
used to generate:
const uint64_t v2_address =
__gen_combine_address(data, &dw[2], values->Pointer, 0);
...
const uint64_t v4_address =
__gen_combine_
With Jason's comment addressed :
Reviewed-by: Lionel Landwerlin
On 20/05/17 08:24, Kenneth Graunke wrote:
This will let us initialize the constant buffers with loops.
---
src/intel/genxml/gen7.xml | 14 ++
src/intel/genxml/gen75.xml
Patches 2-4 are :
Acked-by: Lionel Landwerlin
On 20/05/17 08:24, Kenneth Graunke wrote:
If you have something like:
We would reset ctx->group_count to 0 after processing the first field,
so the second would not have a group count.
This is largely untested,
On 31/05/17 02:04, Ian Romanick wrote:
I've seen this warning a million times, and I always talk myself out of
fixing it. If the type of counterIndex ever changes to int (or another
signed type), this will break. It may not be obvious at the time of the
break that it happened, and it will likel
Hi,
Here is a v2 that applies on top of Ken's series :
https://patchwork.freedesktop.org/series/24739/
Cheers,
Lionel Landwerlin (2):
intel: gen-decoder: rework how we handle groups
genxml/anv: enable MI_LOAD_REGISTER* to load more than 1 register
src/intel/common/gen_decoder.c
ml) (Lionel)
Now that we have proper iteration over count=0 groups, don't let
aubinator overwrite the group_size fields (Lionel
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 226 +++--
src/intel/common/gen_decoder
The kernel already uses that feature and it would be nice to have
aubinator be able to dump those.
Signed-off-by: Lionel Landwerlin
---
src/intel/genxml/gen4.xml | 10 ++--
src/intel/genxml/gen5.xml | 10 ++--
src/intel/genxml/gen6.xml | 10 ++--
src/intel
This series is :
Reviewed-by: Lionel Landwerlin
On 30/05/17 23:08, Rafael Antognolli wrote:
We already have a function to dump sampler states, so do that for gen6
too.
Signed-off-by: Rafael Antognolli
---
src/intel/tools/aubinator.c | 11 +++
1 file changed, 11 insertions
On 05/06/17 23:54, Rafael Antognolli wrote:
realloc() does not initialize the newly added memory, unlike calloc(). So you
can't depend on those new pointers to be zero. It doesn't look like you depend
on that because you have the nfields variable anyways. But if you really don't
care about initi
Reviewed-by: Lionel Landwerlin
On 08/06/17 23:05, Connor Abbott wrote:
From: Connor Abbott
Before, we were just implementing it with a move, which is incorrect
when the source and destination have different bitsizes. To implement
it properly, we need to use the 64-bit pack/unpack opcodes
Patches 1-5 are :
Reviewed-by: Lionel Landwerlin
On 06/06/17 17:23, Rafael Antognolli wrote:
This series converts SF_STATE, COLOR_CALC_STATE adn BLEND_CONSTANT_COLOR state
to use genxml. It has to be applied on top of this series from Ken:
https://patchwork.freedesktop.org/series/24245
Pretty obvious missing break statement.
CID: 1412564
Fixes: 641405f797 "i965: Use the new tracking mechanism for HiZ"
Signed-off-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/driver
needs a trivial rebase fix, otherwise it is:
Reviewed-by: Eduardo Lima Mitev
On 12/02/2016 03:38 PM, Lionel Landwerlin wrote:
This is the size selected by the i965 driver.
Signed-off-by: Lionel Landwerlin
Cc: Kenneth Graunke
---
src/intel/vulkan/anv_private.h | 2 +-
1 file changed, 1
Out of curiosity, does this fix a test (maybe upcoming one)?
Otherwise sounds fair :
Reviewed-by: Lionel Landwerlin
Thanks!
On 14/06/17 17:55, Andres Gomez wrote:
VK_FORMAT_FEATURE_TRANSFER_[SRC|DST]_BIT_KHR is a flag value of the
VkFormatFeatureFlagBits enum that can only be hold and
& i965. Maybe other drivers would be interested and
maybe we should put all the kernel drm uapi headers into include?
Cheers,
Lionel Landwerlin (2):
aubinator: import intel_aub.h from libdrm
anv/i965: drop libdrm_intel dependency completely
configure.ac
This enables us to compile aubinator without the libdrm dependency.
Signed-off-by: Lionel Landwerlin
---
src/intel/tools/intel_aub.h | 153
1 file changed, 153 insertions(+)
create mode 100644 src/intel/tools/intel_aub.h
diff --git a/src/intel
on of libdrm to
have this compile.
Cheers,
[1] : https://patchwork.freedesktop.org/series/25801/
Lionel Landwerlin (6):
intel: common: add flag to identify platforms by name
i965: perf: fix codegen with single operand equation
i965: perf: keep on reading reports until delimiting timestamp
i965
Thanks!
Reviewed-by: Lionel Landwerlin
On 17/10/17 02:09, Jason Ekstrand wrote:
---
src/compiler/nir/nir.c | 22 +++
src/compiler/nir/nir.h | 4
src/compiler/nir/nir_lower_samplers.c| 27
Yeah, it also applies to i965.
I'm guessing we haven't seen that problem because expat gets pulled in
by other bits of the mesa.
Looks good to me, thanks :
Reviewed-by: Lionel Landwerlin
On 17/10/17 02:10, Hongxu Jia wrote:
Linking libvulkan_intel.so can fail, due to unresolved
Reviewed-by: Lionel Landwerlin
On 17/10/17 02:09, Jason Ekstrand wrote:
---
src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
b/src/intel/vulkan
Thanks again!
Reviewed-by: Lionel Landwerlin
On 18/10/17 08:54, Samuel Iglesias Gonsálvez wrote:
v2:
- Use helper to add a new source to the texture instruction.
Signed-off-by: Samuel Iglesias Gonsálvez
---
src/compiler/nir/nir_lower_tex.c | 23 +++
1 file changed, 23
If you feel like it, you could also fix the meson build :)
Otherwise, this is :
Reviewed-by: Lionel Landwerlin
On 18/10/17 02:47, Hongxu Jia wrote:
Linking libvulkan_intel.so can fail, due to unresolved references to
libexpat.so.
EXPAT_CFLAGS should be moved as well.
Signed-off-by: Hongxu
Thanks Eric!
Reviewed-by: Lionel Landwerlin
On 18/10/17 12:08, Eric Engestrom wrote:
Suggested-by: Lionel Landwerlin
Signed-off-by: Eric Engestrom
---
src/intel/common/meson.build | 2 +-
src/intel/tools/meson.build | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a
Signed-off-by: Lionel Landwerlin
---
src/intel/blorp/blorp_blit.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 11c2116a758..4507046dae5 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2206,6
This workaround isn't listed on Gen10.
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/gen8_cmd_buffer.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
b/src/intel/vulkan/gen8_cmd_buffer.c
index f19867ca320..751212b8f43 100644
--- a/src/
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index a4ea7e33d9c..a117e119641 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel
v2: Warn that support is still in alpha (Jason)
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index a305afebc32..67028e8da9f 100644
--- a
Reviewed-by: Lionel Landwerlin
On 27/10/17 13:55, Tapani Pälli wrote:
Patch uses mem_ctx for allocation to ensure param array gets freed
later, in blorp clear case this happens in blorp_params_get_clear_kernel.
==6164== 48 bytes in 1 blocks are definitely lost in loss record 61 of 193
==6164
On 27/10/17 14:46, Emil Velikov wrote:
On 27 October 2017 at 13:55, Tapani Pälli wrote:
Patch uses mem_ctx for allocation to ensure param array gets freed
later, in blorp clear case this happens in blorp_params_get_clear_kernel.
==6164== 48 bytes in 1 blocks are definitely lost in loss record
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 395ff02908a..55e7305117c 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel
It seems nobody's using the string hashing function. If you try to
pass it directly to the hashtable creation function, you'll get
compiler warning for non matching prototypes. Let's make them match.
Signed-off-by: Lionel Landwerlin
---
src/util/hash_table.c | 3 ++-
src/util/h
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index 395ff02908a..55e7305117c 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel
This should be inside the function that actually decodes fields.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_decoder.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder.c
index ef39c1c14db
e find this interesting.
Cheers,
Lionel Landwerlin (33):
intel: common: expose gen_spec fields
intel: common: silence compiler warning
intel: decoder: build sorted linked lists of fields
intel: common: print out all dword with field spanning multiple dwords
intel: decoder: reorder iterato
The xml files don't always have fields in order. This might confuse
our parsing of the commands. Let's have the fields in order. To do
this, the easiest way it to use a linked list. It also helps a bit
with the iterator.
Signed-off-by: Lionel Landwerlin
---
src/intel/common/gen_deco
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