Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 2 ++
src/mesa/drivers/dri/i965/brw_device_info.c | 22 ++
2 files changed, 24 insertions(+)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids
From: Ben Widawsky
The stated bug describes a scenario in which a post sync write operation for
depth or timestamp can be ignored. There are two workarounds suggested, the
first and easier is to simply do a cs stall when we do these type of writes.
The second option is to do a PIPE_CONTROL flush
TENCIL(dev) == dev->use_separate_stencil);
Signed-off-by: Ben Widawsky
---
src/intel/isl/isl.c | 4 ++--
src/intel/isl/isl.h | 8
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index e4bca16..77b570d 100644
--- a/src/intel/
On Wed, Jun 08, 2016 at 11:28:12AM -0700, Anuj Phogat wrote:
> An update in graphics specs has deleted the halign and valign fields
> from XY_FAST_COPY_BLT command. See mesa commit 97f0f91.
>
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
Reviewed-by: Ben Widawsky
> ---
&
On Fri, Nov 13, 2015 at 12:22:47PM -0800, Chad Versace wrote:
> On Wed 11 Nov 2015, Ben Widawsky wrote:
> > Some of the information originally in this commit message is now in the
> > patch
> > before this.
> >
> > SKL adds compressible render targets an
On Fri, Nov 13, 2015 at 12:29:47PM -0800, Chad Versace wrote:
> On Wed 11 Nov 2015, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as auxiliary data in
> > "comp
This helps address a coverity warning and prevents future questions about this
code.
Reported-by: Coverity (via Ilia)
Cc: Matt Turner
Cc: Ilia Mirkin
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers
On Tue, Nov 17, 2015 at 11:28:25AM -0800, Kristian Høgsberg wrote:
> On Tue, Nov 17, 2015 at 11:25 AM, Kenneth Graunke
> wrote:
> > We basically just need to uncomment Ben's code.
>
> Reviewed-by: Kristian Høgsberg
>
umentation:
> +*
> +* "URB is limited to 1008KB due to programming restrictions. This
> +* is not a restriction of the L3 implementation, but of the FF and
> +* other clients. Therefore, in a GT4 implementation it is
> +* possible for the programmed alloca
BYLAKE(devid) (IS_KBL_GT1(devid) || \
> + IS_KBL_GT2(devid) || \
> + IS_KBL_GT3(devid) || \
> + IS_KBL_GT4(devid))
> +
The actual correct breakdown IMO (and the encoding going back to bdw) is ni
On Sat, Nov 14, 2015 at 01:43:41PM -0800, Jordan Justen wrote:
> From: Francisco Jerez
>
> It should be possible to use additional L3 configurations other than
> the ones listed in the tables of validated allocations ("BSpec »
> 3D-Media-GPGPU Engine » L3 Cache and URB [IVB+] » L3 Cache and URB [
ession Requested-by: Chad
- change meaning of brw_losslessly_compressible_format Requested-by: Chad
- related changes to the code to reflect this.
- remove excess ccs (Chad)
Requested-by: Chad Versace
Requested-by: Neil Roberts
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_context.h
e they are now
handled by Neil's patch to disable MSAA fast clears.
Cc: Neil Roberts
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 8 ++--
src/mesa/drivers/dri/i965/gen8_surface_state.c | 8
2 files changed, 6 insertions(+), 10 deletions(-)
d
had. I didn't even look at it since Chad said
he was fine with that, and presumably Matt is fine with it.
Cc: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 52 -
src/mesa/drivers/dri/i965/gen8_surface_state.c | 8
On Wed, Nov 18, 2015 at 11:10:12AM +0200, Pohjolainen, Topi wrote:
> On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as au
On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote:
> On Tue 17 Nov 2015, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as auxiliary data in
> > "comp
On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote:
> On Tue 17 Nov 2015, Ben Widawsky wrote:
> > Background: Prior to Skylake and since Ivybridge Intel hardware has had the
> > ability to use a MCS (Multisample Control Surface) as auxiliary data in
> > "comp
On Wed, Nov 18, 2015 at 12:15:40PM +0200, Pohjolainen, Topi wrote:
> On Tue, Nov 17, 2015 at 05:31:12PM -0800, Ben Widawsky wrote:
> > Some of the information originally in this commit message is now in the
> > patch
> > before this.
> >
> > SKL adds compressib
On Wed, Nov 18, 2015 at 03:50:32PM -0800, Ben Widawsky wrote:
> On Wed, Nov 18, 2015 at 11:10:12AM +0200, Pohjolainen, Topi wrote:
> > On Tue, Nov 17, 2015 at 05:30:06PM -0800, Ben Widawsky wrote:
> > > Background: Prior to Skylake and since Ivybridge Intel hardware
order (BGRX).
BTW, I pointed this out to Nanley, but I didn't see a patch, I think we need to
add is_braswell (and maybe broxton)) to the gen += 5 at the top of this
function.
lgtm
Reviewed-by: Ben Widawsky
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_state == INTEL_FAST_CLEAR_STATE_NO_MCS)
I forget, did you find failures for this in the non-MSRT case? If not, maybe we
could skip this patch and just take the rest of the series? That way we can
avoid the "perf regression" of RGBX clears which we do hit on certain workloads.
Assuming we have a failure in non-MSRT case, and we can't just bypass this
patch, this is:
Reviewed-by: Ben Widawsky
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On Thu, Nov 19, 2015 at 04:25:19PM +0100, Neil Roberts wrote:
> The tiled memcpy doesn't work for copying from RGBX to RGBA because it
> doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added
> a check to disable it for RGBX formats by looking at the TexFormat.
> However a lot of th
On Thu, Nov 19, 2015 at 04:25:21PM +0100, Neil Roberts wrote:
> The RGBX surface formats aren't renderable so we internally remap them
> to RGBA when rendering. They are retained as RGBX when used as
> textures. However since the previous patch fast clears are disabled
> for surfaces that use a dif
On Fri, Nov 20, 2015 at 02:18:56PM +, Emil Velikov wrote:
> On 18 November 2015 at 21:59, Ilia Mirkin wrote:
> > On Wed, Nov 18, 2015 at 4:54 PM, Sarah Sharp
> > wrote:
> >>> There's not really a consensus I guess, but most people do leave the
> >>> version
> >>> information in the final com
On Fri, Nov 20, 2015 at 11:02:43AM -0800, Chad Versace wrote:
> On Wed 18 Nov 2015, Ben Widawsky wrote:
> > On Wed, Nov 18, 2015 at 10:28:27AM -0800, Chad Versace wrote:
> > > On Tue 17 Nov 2015, Ben Widawsky wrote:
> > > > Background: Prior to Skylake and since Iv
mp; mt->num_samples > 1) {
>aux_mt = mt->mcs_mt;
>aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
>
--
Ben Widawsky, Intel Open Source Technology Center
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iled).
>
> All of my SKL fast clear patches are in a branch here:
>
> https://github.com/bpeel/mesa/commits/skl-fast-clear
>
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The most important feedback I have on the patch is that we continue to add stuff
like this for compute when there is a libdrm interface which exposes all or most
of it - and that interface should either be expanded or removed. FWIW, I wasn't
a big fan of the interface when it was introduced, but it
As per the docs.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index ae3d818
On Wed, Dec 23, 2015 at 12:09:44PM -0800, Anuj Phogat wrote:
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_state_dump.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_
While working in this part of the code I had a great deal of trouble
understanding what it was trying to do, and matching it with the spec.
(mostly due bad wording in the PRM). To help future people, I've cleaned
up the wording and provided some ascii art.
---
src/mesa/drivers/dri/i965/gen8_viewpo
On GEN8, a change in scissor state does not effect anything for the
clipper/sf hardware state. The hardware will always do the right thing
once the viewport extents are programmed. We can therefore remove the
unecessary state emission.
Ken originally spotted this.
---
src/mesa/drivers/dri/i965/ge
The goal of guardband clipping is to try to avoid 3d clipping because it
is an expensive operation. When guardband clipping is disabled, all
geometry that intersects the viewport is to the FF 3d clipper. Objects
which are entirely enclosed within the viewport are said to be
"trivially accepted" whi
that).
Ben Widawsky (4):
i965/guardband: Improve comments for guardband clipping
i965: Viewport extents on GEN8
i965/guardband: Enable for all viewport dimensions (GEN8+)
i965/clip: Removing scissor atom
src/mesa/drivers/dri/i965/gen6_clip_state.c | 29 +-
src/mesa
Viewport extents are a 3rd rectangle that defines which pixels get
discarded as part of the rasterization process. This can potentially
improve performance by reducing cache usage, and freeing up PS cycles.
It also permits the use of guardband clipping in all cases (see later
patch). The actual pix
I realize it hasn't even been a week yet, but my remaining 2 weeks until
my sabbatical have just filled up, so if anyone needs me to rework this,
the sooner you let me know the better.
On Mon, Aug 04, 2014 at 12:24:00PM -0700, Ben Widawsky wrote:
> The patch commit messages and comment
On Sat, Aug 09, 2014 at 12:07:58PM -0700, Ben Widawsky wrote:
> I realize it hasn't even been a week yet, but my remaining 2 weeks until
> my sabbatical have just filled up, so if anyone needs me to rework this,
> the sooner you let me know the better.
Hi Ken. Thanks a lot for r
ich
> GRF start offsets to use, so lets figure out these two things in one place.
>
> Signed-off-by: Kristian Høgsberg
Some nits inline, but it looks okay to me otherwise.
Reviewed-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/gen6_wm_state.c | 16
>
8 },
> { NULL,0 }
> };
>
> diff --git a/src/mesa/drivers/dri/i965/intel_debug.h
> b/src/mesa/drivers/dri/i965/intel_debug.h
> index 37dc34a..8e1c299 100644
> --- a/src/mesa/drivers/dri/i965/intel_debug.h
> +++ b/src/mesa/drivers/dri/i965/intel_debug.h
> @@ -62,6
t; +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
> @@ -217,7 +217,8 @@ do_gs_prog(struct brw_context *brw,
> /* URB entry sizes are stored as a multiple of 64 bytes. */
> c.prog_data.base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
>
> -
On Mon, Aug 11, 2014 at 10:40:25PM -0700, Kenneth Graunke wrote:
> On Monday, August 11, 2014 07:53:11 PM Ben Widawsky wrote:
> > On Mon, Aug 11, 2014 at 05:29:31PM -0700, Kristian Høgsberg wrote:
> [snip]
> > > diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> &g
On Mon, Aug 11, 2014 at 11:18:36PM -0700, Ben Widawsky wrote:
> On Mon, Aug 11, 2014 at 10:40:25PM -0700, Kenneth Graunke wrote:
> > On Monday, August 11, 2014 07:53:11 PM Ben Widawsky wrote:
> > > On Mon, Aug 11, 2014 at 05:29:31PM -0700, Kristian Høgsberg wrote:
> > [sn
[4] This was the best I could do on short notice. I won't be improving,
rebasing, or fixing these patches any longer, but someone is welcome to take
them over. Consider this my parting gift before I go on sabbatical [tomorrow].
--
Ben Widawsky (68):
drm/i915: Split up do_switch
drm/i91
This was a quick proof of concept to show the new API for prelocating
buffers.
It needs way more testing, to not ifdef the no-relocs, and to do a
libdrm ABI dep bump.
---
src/mesa/drivers/dri/i965/Makefile.am | 1 +
src/mesa/drivers/dri/i965/brw_performance_monitor.c | 6 +++---
src
On Fri, Aug 22, 2014 at 08:15:28AM -0400, Alex Deucher wrote:
> On Thu, Aug 21, 2014 at 11:12 PM, Ben Widawsky
> wrote:
> > This was a quick proof of concept to show the new API for prelocating
> > buffers.
> >
>
> What are prelocated buffers?
http://lists.freedesk
18:17, Ben Widawsky wrote:
Could do smarter stuff with the mappings. I decided not to.
Tested with kmscube. No current clients seem to use non-zero x0, y0, so
that's untested.
Cc: Tapani Pälli (AndroidIA?)
Tomasz, Tapani,
With this in place you should be able to drop the [patched] 3.
On 17-07-07 09:28:08, Jason Ekstrand wrote:
On Thu, Jul 6, 2017 at 4:27 PM, Ben Widawsky wrote:
We don't yet have optimal MOCS settings, but we have enough to know how
to at least determine when we might have non-optimal settings within our
driver.
Signed-off-by: Ben Widawsky
---
src/
_LINEAR 0
-#endif
-
static const __DRIconfigOptionsExtension brw_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
Both are:
Reviewed-by: Ben Widawsky
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mesa
Could do smarter stuff with the mappings. I decided not to.
Tested with kmscube. No current clients seem to use non-zero x0, y0, so
that's untested.
Cc: Tapani Pälli (AndroidIA?)
Cc: Emil Velikov
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c
t;Otherwise" is certainly not okay, but I like this. Feel free to nak of course.
Acked-by: Ben Widawsky
On April 24, 2017 6:16:14 PM Emil Velikov wrote:
From: Emil Velikov
To ease patch submission process a tiny bit.
Cc: Ben Widawsky
Suggested-by: Ben Widawsky
Signed-off-by: Emil Vel
From: Ben Widawsky
V2: Squash the changes in one patch and rebased on master (Anuj).
Signed-off-by: Ben Widawsky
Signed-off-by: Anuj Phogat
---
src/intel/common/gen_l3_config.c | 43 ++--
1 file changed, 37 insertions(+), 6 deletions(-)
diff --git a/src/
On 17-04-15 18:27:33, Jason Ekstrand wrote:
On April 14, 2017 5:37:55 PM Anuj Phogat wrote:
From: Ben Widawsky
This support was removed on gen9 (it worked before then) and was brought back
for gen10.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +-
1
On 17-04-25 14:53:46, Anuj Phogat wrote:
On Mon, Apr 24, 2017 at 10:57 PM, Ben Widawsky wrote:
On 17-04-15 18:27:33, Jason Ekstrand wrote:
On April 14, 2017 5:37:55 PM Anuj Phogat wrote:
From: Ben Widawsky
This support was removed on gen9 (it worked before then) and was brought
back
Fix kmscube -A on i915 :P
On 17-04-28 14:17:34, Rob Clark wrote:
I guess this applies on top of one of Ben's in-flight patches?
Perhaps it can be squashed into that? (Otherwise remind me about this
when the modifiers patchset is merged)
BR,
-R
On Fri, Apr 28, 2017 at 12:18 PM, Lucas Stach wr
On 17-05-02 11:51:28, Francisco Jerez wrote:
Anuj Phogat writes:
On Mon, Apr 24, 2017 at 9:15 PM, Ben Widawsky wrote:
On 17-04-18 18:18:39, Francisco Jerez wrote:
Most, if not all of the unrelated changes that snuck in were due to rebase.
Anuj, would you mind fixing those? I tried my best
On 17-05-10 23:15:29, Varad Gautam wrote:
From: Ben Widawsky
Modifiers will be obtained or guessed by the client and passed in during
image creation/import.
As of this patch, the modifiers aren't plumbed all the way down, this
patch simply makes sure the interface level stuff is correc
From: Ben Widawsky
Starting with GEN9, Memory Object Control State (MOCS) becomes an index
into a table as opposed to the direct programming within the command.
The table has 62 usable entries (ie 6 bits can represent all settings),
and each buffer type may use one of these 62 entries to
Signed-off-by: Ben Widawsky
---
src/intel/drm/i915_drm.h | 8
1 file changed, 8 insertions(+)
diff --git a/src/intel/drm/i915_drm.h b/src/intel/drm/i915_drm.h
index c26bf7c125..69e38ce89f 100644
--- a/src/intel/drm/i915_drm.h
+++ b/src/intel/drm/i915_drm.h
@@ -431,6 +431,14 @@ typedef
We don't yet have optimal MOCS settings, but we have enough to know how
to at least determine when we might have non-optimal settings within our
driver.
Signed-off-by: Ben Widawsky
---
src/intel/vulkan/anv_device.c | 12
src/intel/vulkan/anv_private.h
mmit c9b0481bce24af032386701de0266eb5bc24e988
Author: Ben Widawsky
Date: Fri Apr 8 10:21:16 2016 -0700
i965: Use PTE mocs
Signed-off-by: Ben Widawsky
diff --git a/src/mesa/drivers/dri/i965/brw_mocs.c
b/src/mesa/drivers/dri/i965/brw_mocs.c
index 5df154eb86..b7bfdab671 100644
--- a/s
On 17-07-07 11:34:48, Chris Wilson wrote:
Quoting Ben Widawsky (2017-07-07 00:27:01)
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 13 +
include/uapi/drm/i915_drm.h | 8
4 files changed, 22
On 17-07-07 09:23:26, Jason Ekstrand wrote:
On Fri, Jul 7, 2017 at 3:34 AM, Chris Wilson
wrote:
Quoting Ben Widawsky (2017-07-07 00:27:01)
> drivers/gpu/drm/i915/i915_drv.c | 3 +++
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
drivers/gpu/drm/i915/i915_pci.c | 13 +
>
On 17-12-18 15:23:11, Antognolli, Rafael wrote:
We still have gpu hangs on Cannonlake when using push constants, so
disable them for now until we have a proper fix for these hangs.
v2: Add warning message when creating context too.
Signed-off-by: Rafael Antognolli
Cc: Ben Widawsky
Cc
On 16-12-02 09:43:07, Daniel Stone wrote:
Hi Ben,
On 1 December 2016 at 22:09, Ben Widawsky wrote:
@@ -678,6 +679,28 @@ gbm_dri_bo_get_offset(struct gbm_bo *_bo, int plane)
return (uint32_t)offset;
}
+static uint64_t
+gbm_dri_bo_get_modifier(struct gbm_bo *_bo)
+{
+ struct
On 16-12-16 21:27:51, Rainer Hochecker wrote:
From: Rainer Hochecker
This allows eglCreateImageKHR to access P010 surfaces created by vaapi
patch for drm, fourcc:
http://paste.ubuntu.com/23638632/
Signed-off-by: Rainer Hochecker
---
include/GL/internal/dri_interface.h | 4
src/egl/
On 16-12-06 13:34:02, Paulo Zanoni wrote:
2016-12-01 20:09 GMT-02:00 Ben Widawsky :
From: Ben Widawsky
This patch series ultimately adds support within the i965 driver for
Renderbuffer Decompression with GBM. In short, this feature reduces memory
bandwidth by allowing the GPU to work with
On 16-12-10 15:26:02, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:09:57PM -0800, Ben Widawsky wrote:
From: Ben Widawsky
This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.
Primarily this patch is split out for review, it can be
On 16-12-29 17:34:19, Ben Widawsky wrote:
On 16-12-06 13:34:02, Paulo Zanoni wrote:
2016-12-01 20:09 GMT-02:00 Ben Widawsky :
From: Ben Widawsky
This patch series ultimately adds support within the i965 driver for
Renderbuffer Decompression with GBM. In short, this feature reduces memory
On 16-12-10 15:36:06, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:09:58PM -0800, Ben Widawsky wrote:
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 37
1 file changed, 33 insertions(+), 4 deletions
On 16-12-10 15:39:12, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:09:59PM -0800, Ben Widawsky wrote:
From: Ben Widawsky
There is nothing particularly useful to do currently if the update
fails, but there is no point carrying on either. As a result, this has a
behavior change.
Signed
On 16-12-31 14:40:42, Ben Widawsky wrote:
On 16-12-10 15:39:12, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:09:59PM -0800, Ben Widawsky wrote:
[snip]
We don't seem to use "zero for success"-style at least in i965. Could you
change this to bool and flip the ch
On 16-12-10 16:05:12, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:10:01PM -0800, Ben Widawsky wrote:
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_screen.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a
On 16-12-10 16:24:46, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:10:06PM -0800, Ben Widawsky wrote:
From: Ben Widawsky
On Gen9 hardware, the display engine is able to scanout a compressed
framebuffer by providing an offset to auxiliary compression information.
Unfortunately, the
On 16-12-11 10:05:25, Pohjolainen, Topi wrote:
On Thu, Dec 01, 2016 at 02:10:07PM -0800, Ben Widawsky wrote:
From: Ben Widawsky
Cc: Topi Pohjolainen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions
1c8be049bea786c2c054a770025976beba5b8636
Author: Chad Versace
Date: Fri Dec 9 16:18:11 2016 -0800
i965/mt: Disable aux surfaces after making miptree shareable
The next patch will handle CCS and get rid of no_ccs.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 24
Cc: Topi Pohjolainen
Cc: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
src/mesa/drivers/dri/i965/brw_draw.c | 3 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 ++---
src/mesa/drivers/dri/i965
On 17-01-02 10:25:49, Topi Pohjolainen Topi Pohjolainen wrote:
On Thu, Dec 29, 2016 at 05:41:49PM -0800, Ben Widawsky wrote:
On 16-12-10 15:26:02, Pohjolainen, Topi wrote:
> On Thu, Dec 01, 2016 at 02:09:57PM -0800, Ben Widawsky wrote:
> > From: Ben Widawsky
> >
> > T
On 16-12-02 17:57:40, Eric Engestrom wrote:
On Thursday, 2016-12-01 14:09:44 -0800, Ben Widawsky wrote:
From: Ben Widawsky
This will be used by clients that need to know the number of planes
allocated for them on behalf of the GL or other API. The best current
example of this is when an extra
On 16-12-02 17:58:40, Eric Engestrom wrote:
On Thursday, 2016-12-01 14:09:45 -0800, Ben Widawsky wrote:
From: Ben Widawsky
This will be used so we can query information per plane.
Signed-off-by: Ben Widawsky
---
src/gbm/backends/dri/gbm_dri.c | 7 +++
src/gbm/main/gbm.c | 2
On 16-12-02 18:01:02, Eric Engestrom wrote:
On Thursday, 2016-12-01 14:09:49 -0800, Ben Widawsky wrote:
From: Ben Widawsky
Modifiers will be obtains or guessed by the client and passed in during
image creation/import.
This requires bumping the DRIimage version.
Signed-off-by: Ben Widawsky
v2: Other way round... to make consistent, make both return type have
the fixed width - uint32_t.
Cc: Daniel Stone
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/gbm/main/gbm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src
Signed-off-by: Ben Widawsky
Reviewed-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa
Other things are out of order, but I need to add a getter so I'm just
fixing those.
This helps people adding to GBM know where the right place to put things
is.
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/gbm/main/gbm.c
d a couple from
the original).
Ben Widawsky (32):
i965: Fix SURFACE_STATE to handle non-zero aux offsets
gbm: Move getters to match order in header file (trivial)
gbm: Fix width height getters return type (trivial)
gbm: Export a plane getter function
gbm: Export a getter for per plane han
llow usage + modifiers
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
include/GL/internal/dri_interface.h | 27 +-
src/gallium/state_trackers/dri/dri2.c| 1 +
src/mesa/drivers/dri/i965/intel_scr
This will be used by clients that need to know the number of planes
allocated for them on behalf of the GL or other API. The best current
example of this is when an extra "plane" is allocated to store
compression data for the primary plane.
Cc: Daniel Stone
Signed-off-by: Ben Widawsky
Unlike stride, there was no previous offset getter, so it can be right
on the first try.
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/gbm/backends/dri/gbm_dri.c | 27 +++
src/gbm/gbm-symbols-check | 1 +
src/gbm/main
I intend to need to get to the devinfo structure, and storing the screen
is an easy way to do that.
It seems to be the consensus that you cannot share an image between
multiple screens.
Scape-goat: Rob Clark
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
Cc: Daniel Stone
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/gbm/backends/dri/gbm_dri.c | 28
src/gbm/gbm-symbols-check | 1 +
src/gbm/main/gbm.c | 18 ++
src/gbm/main/gbm.h | 3 +++
src/gbm/main
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/gbm/backends/dri/gbm_dri.c | 26 +-
src/gbm/gbm-symbols-check | 1 +
src/gbm/main/gbm.c | 15 ++-
src/gbm/main/gbm.h | 3 +++
4 files
v2: Use stored modifiers from create instead of queryImage
v3: Make sure not to query modifiers for dumb buffers (Daniel)
Discussion with Kristian yielded that there is no need for per plane
modifiers.
Cc: Daniel Stone
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel
st X
tiled.
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index b867c28cae..2e0c9922
This doesn't actually enable Y-tiling, it simply parses it and moves on.
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_image.h | 1 +
src/mesa/drivers/dri/i965/intel_screen.c | 36 +---
2
Since the code doesn't support modifiers yet, this patch should do
nothing other than prepare for more patches.
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 73 ++--
1 file changed, 60 insertions(+), 13 dele
This will be used so we can query information per plane.
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/gbm/backends/dri/gbm_dri.c | 7 +++
src/gbm/main/gbm.c | 2 +-
src/gbm/main/gbmint.h | 1 +
3 files changed, 9 insertions
ck if count is non-zero in addition to testing if
calloc fails. (Daniel)
v3: Remove "usage" and "flags" from modifier creation. Requested by
Kristian.
Cc: Kristian Høgsberg
Cc: Daniel Stone
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
commit 6a0d036483caf87d43ebe2edd1905873446c9589
Author: Ben Widawsky
Date: Thu Apr 21 20:14:58 2016 -0700
i965: Always use Y-tiled buffers on SKL+
Aside from the benchmark gains that were initially posted, I was able to
collect memory bandwidth data running kmscube (19x12 display
n aux offset possible.
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_image.h | 3 +++
src/mesa/drivers/dri/i965/intel_screen.c | 5 +
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_image.h
b/src/mesa/drivers/dri
ectly.
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index ba968bee17..153542c1d1 100644
This patch adds support for handling X tiled modifier. This isn't
particularly useful but it makes our code complete.
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --
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