On 17-01-31 11:40:04, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:19 PM, Ben Widawsky wrote:
Unlike stride, there was no previous offset getter, so it can be right
on the first try.
v2: Return EINVAL when plane is greater than total planes to make it
match the similar APIs.
Avoid leak
On 17-01-31 12:38:44, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
Replace the naive, 'save all the modifiers' with a proper query for just
the modifier that was selected. To accomplish this, two new query tokens
are added to the
Jason's recommended change)
Make plane 0 return planar stride. This might break legacy behavior (Jason)
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom (v1)
Acked-by: Daniel Stone
make plane 0 with multi plane be normal (Jason)
---
src/gbm/backends/dri/g
Jason's recommendation for handling the non-planar case.
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
Reviewed-by: Eric Engestrom
Acked-by: Daniel Stone
---
src/gbm/backends/dri/gbm_dri.c | 33 +
src/gbm/gbm-symbols-check | 1 +
src/gbm/main/
On 17-01-31 11:52:38, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
The idea behind modifiers like this is that the user of GBM will have
some mechanism to query what properties the hardware supports for its BO
or surface. This information is directly passed in
t bother with storing modifiers for gbm_bo_create because that's
a synchronous operation and we can actually select the correct modifier
at create time (done in a later patch) (Jason)
Cc: Kristian Høgsberg
Cc: Jason Ekstrand
References (v4):
https://lists.freedesktop.org/archives/intel-gfx/201
On 17-01-31 12:10:11, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
This patch begins introducing how we'll actually handle the potentially
many modifiers coming in from the API, how we'll store them, and the
structure in the code to support it.
Pri
On 17-01-31 13:01:11, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
Since the code doesn't support modifiers yet, this patch should do
nothing other than prepare for more patches.
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/driver
On 17-01-31 12:54:33, Jason Ekstrand wrote:
On Wed, Jan 25, 2017 at 10:58 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:
On Mon, Jan 23, 2017 at 10:21:41PM -0800, Ben Widawsky wrote:
> This provides a common function or creating miptrees when there is an
> existing DRI
On 17-01-25 20:53:44, Topi Pohjolainen Topi Pohjolainen wrote:
On Mon, Jan 23, 2017 at 10:21:43PM -0800, Ben Widawsky wrote:
Make the code only disable CCS when it has to, unlike before where it
disabled CCS and enabled it when it could. This is much more inline with
how it should work in a few
ectly.
v2: Do proper alignment for X tiling, and make sure non-tiled case is
handled (Jason)
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/driver
On 17-01-31 13:03:52, Jason Ekstrand wrote:
On Wed, Jan 25, 2017 at 10:36 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:
On Mon, Jan 23, 2017 at 10:21:46PM -0800, Ben Widawsky wrote:
> This patch provides the support (and comments) for allocating the BO
> with space
On 17-02-06 10:00:16, Topi Pohjolainen Topi Pohjolainen wrote:
On Sun, Feb 05, 2017 at 10:48:11PM -0800, Ben Widawsky wrote:
On 17-01-25 20:53:44, Topi Pohjolainen Topi Pohjolainen wrote:
> On Mon, Jan 23, 2017 at 10:21:43PM -0800, Ben Widawsky wrote:
> > Make the code only disable CC
On 17-02-14 13:45:48, Kenneth Graunke wrote:
This is more convenient than OUT_BATCH'ing both halves.
It also is potentially more efficient (probably immeasurable).
Reviewed-by: Ben Widawsky
Signed-off-by: Kenneth Graunke
Cc: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_depth_st
On 17-01-31 13:16:24, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965/intel_screen.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/src/mesa
On 17-01-31 13:24:55, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
v2: Put the commit message as a comment (Topi)
Cc: Topi Pohjolainen
Cc: Ville Syrjälä
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
Acked-by: Daniel Stone
---
src/mesa/drivers/dri/i965
On 17-02-27 18:40:41, Jason Ekstrand wrote:
On Mon, Feb 27, 2017 at 5:38 PM, Jason Ekstrand
wrote:
On Mon, Feb 27, 2017 at 4:56 PM, Ben Widawsky wrote:
On 17-01-31 13:24:55, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
v2: Put the commit message as a
On 17-01-31 13:37:25, Jason Ekstrand wrote:
On Wed, Jan 25, 2017 at 10:39 AM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:
On Mon, Jan 23, 2017 at 10:21:54PM -0800, Ben Widawsky wrote:
> On Gen9 hardware, the display engine is able to scanout a compressed
> framebuffer
On 17-02-01 09:30:21, Topi Pohjolainen Topi Pohjolainen wrote:
On Tue, Jan 31, 2017 at 01:37:25PM -0800, Jason Ekstrand wrote:
On Wed, Jan 25, 2017 at 10:39 AM, Pohjolainen, Topi
<[1]topi.pohjolai...@gmail.com> wrote:
On Mon, Jan 23, 2017 at 10:21:54PM -0800, Ben Widawsky
On 17-01-31 13:40:01, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
FINISHME: Use the kernel's final choice for the fb modifier
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $)
~/scripts/measure_bandwidth.sh ./kmscube none
Read bandwidth: 603.91 MiB/s
On 17-02-26 19:19:39, Emil Velikov wrote:
On 11 January 2017 at 15:43, Ben Widawsky wrote:
On 17-01-05 16:58:56, Rainer Hochecker wrote:
From: Rainer Hochecker
This allows eglCreateImageKHR to access P010 surfaces created by vaapi
Signed-off-by: Rainer Hochecker
Acked-by: Ben Widawky
This is easily accomplished by moving simd16 3src to GEN9_FEATURES.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965
On Tue, Jul 28, 2015 at 11:08:39PM -0700, Kenneth Graunke wrote:
> On Tuesday, July 28, 2015 08:00:54 PM Ben Widawsky wrote:
> > This is easily accomplished by moving simd16 3src to GEN9_FEATURES.
> >
> > Signed-off-by: Ben Widawsky
> > ---
> > src/mesa/drive
pushed this before I noticed this mail (I reconfigured my spam
stuff recently and I have a bunch of mails going to spam). I apologize for
missing your r-b; thanks for testing and reviewing though.
>
> Ben Widawsky writes:
>
> > This is easily accomplished by moving simd16 3src to GEN9_
(second hunk) entirely.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965
This patch replaces the previous patch listed in references.
References: http://patchwork.freedesktop.org/patch/54099/
Recommended-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen6_constant_state.c | 104 ++--
1 file changed, 62 insertions
Recommended-by: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/gen6_constant_state.c | 189
src/mesa/drivers/dri/i965/gen6_vs_state.c | 88 ---
src/mesa/drivers/dri/i965
Update:
I no longer thing we should merge this patch. A note in the programming has been
introduced stating that we should not program this state packet without enabling
at least one component.
On Wed, Jul 01, 2015 at 04:06:54PM -0700, Ben Widawsky wrote:
> We don't yet have a use for th
sense
wrt to stable backport as HS, and DS do not even exist there.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_device_info.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa
s not care about hs, and ds. It does care
about cs, but since Jordan was the one that asked me to extract it, I'll leave
it up to him to deal with a backport to stable is required.
Signed-off-by: Ben Widawsky
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_device_info.c | 10 +++
of
having early support is to enable as many configurations that can possibly
exist (we can trim things down after platforms begin shipping later).
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 6 --
1 file changed, 4 insertions(+), 2
needed for other expression types.
>
> Signed-off-by: Chris Forbes
> Cc: Ben Widawsky
Tested-by: Ben Widawsky
I'm not familiar with this code. I can review it if needed, but I'd prefer not
to if there is someone better equipped.
> ---
> src/glsl/ast_function.cpp | 15 +
> -#define MIPTREE_LAYOUT_ALLOC_ANY_TILED (MIPTREE_LAYOUT_ALLOC_YTILED | \
> -MIPTREE_LAYOUT_ALLOC_XTILED)
> -
> struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw,
> GLenum target,
>
On Tue, Aug 04, 2015 at 11:16:55PM -0700, Matt Turner wrote:
> On Tue, Aug 4, 2015 at 11:18 PM, Matt Turner wrote:
> > Regression since commit 3a31876600, when tiling modes were moved into
> > layout_flags.
> >
It be interesting to find out why this caused the perf regression.
> > The relevant en
GLenum target,
> mesa_format format,
>
This is going further in the wrong direction in my opinion (it mimics the old
code more closely, but that that wasn't my original goal). "LINEAR" is not a
tiled type. However,
0, MIPTREE_LAYOUT_ALLOC_LINEAR);
>
> if (!map->mt) {
> fprintf(stderr, "Failed to allocate blit temporary\n");
Reviewed-by: Ben Widawsky
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>
> static void
> diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> index 6ebf381..d3fb252 100644
> --- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
> +++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
> @@ -137,7 +137,7 @@ intel_finalize_mipmap_tree(struct brw_context *brw,
> GLuint unit)
> width, height, depth, validate_last_level + 1);
>
>const uint32_t layout_flags = MIPTREE_LAYOUT_ACCELERATED_UPLOAD |
> -MIPTREE_LAYOUT_ALLOC_ANY_TILED;
> +MIPTREE_LAYOUT_TILING_ANY;
>intelObj->mt = intel_miptree_create(brw,
>intelObj->base.Target,
> firstImage->base.Base.TexFormat,
Reviewed-by: Ben Widawsky
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On Thu, Aug 06, 2015 at 11:39:04AM -0700, Matt Turner wrote:
> On Thu, Aug 6, 2015 at 11:14 AM, Ben Widawsky wrote:
> > On Thu, Aug 06, 2015 at 11:03:55AM -0700, Matt Turner wrote:
> >> Ben suggested that I rename MIPTREE_LAYOUT_ALLOC_ANY_TILED since it
> >> needed
SKL values instead of
early ones (a hopefully irrelevant improvement IMO).
Cc: Jason Ekstrand
Cc: Neil Roberts
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/mesa/driver
On Sun, Aug 09, 2015 at 04:29:33PM -0700, Kenneth Graunke wrote:
> On Friday, August 07, 2015 01:58:37 PM Ben Widawsky wrote:
> > We do not want bug reports from this early stepping of SKL. Few if any were
> > ever
> > shipped outside of Intel to early enabling partners,
On Mon, Aug 10, 2015 at 09:09:41AM -0700, Jason Ekstrand wrote:
> On Aug 10, 2015 4:14 AM, "Neil Roberts" wrote:
> >
> > If we go with this patch perhaps it would be good to remove
> > supports_simd16_3src entirely from brw_device_info and any code that is
> > referring to it in order to avoid car
v2: Rebased. Some manual intervention required.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 6 --
src/mesa/drivers/dri/i965/intel_blit.c| 10 ++
src/mesa/drivers/dri/i965/intel_blit.h| 3 +++
src/mesa/drivers/dri/i965
j pushed since I originally
authored the patch.
commit 524a729f68c15da3fc6c42b3158a13e0b84c2728
Author: Anuj Phogat
Date: Tue Feb 17 10:40:58 2015 -0800
i965: Fix condition to use Y tiling in blitter in intel_miptree_create()
v3: Removed the check against X-tiling since its removal in
9f78e27fc60b3473b708ab4ca04e4ebd6be6cf
well
Batch7 -1.14%
HdrBloom -.94%
ShMapPcf .01%
TerrainFlyInst 17.32%
TerrainPanInst 9.67%
VSDiffuse1.05%
fill (from gfxbench) .08%
---
Ben Widawsky (6):
i965: Kill y_or_x variable in miptree tiling selection
i965
l rebase
References: http://patchwork.freedesktop.org/patch/38909/
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 20 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
src/mesa/drivers/dri/i965/inte
:
> Destination Y2 Coordinate (Bottom)
> 16 bit signed number.
v2: Rebase; conflicts resolved with wiggle
Signed-off-by: Ben Widawsky
Reviewed-by: Neil Roberts
---
src/mesa/drivers/dri/i965/intel_blit.c | 8 ++--
src/mesa/drivers/dri/i965/intel_copy_image.c | 8 ++--
2 files chang
on)
v4:
Make linear height be a page
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 101 +++--
src/mesa/drivers/dri/i965/intel_blit.h | 24 +++-
2 files changed, 118 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/inte
esn't change all places which check blitter requirements. I
will be adding those as a separate patch(es) since the original series, which
was well tested, did not include those.
This was requested by Jordan and Jason.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_b
7;t make any sense of how it related to
a GPU hang.
In any event, I don't think the comments are super useful, but they're not
harmful either. I'd suggest one line instead:
"NOTE: push_constant_ff must precede binding table pointer upload"
Reviewed-by: Ben Widawsky
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On Thu, Aug 13, 2015 at 10:38:43AM +0300, Joonas Lahtinen wrote:
> Hi,
>
> On ke, 2015-08-12 at 18:34 -0700, Ben Widawsky wrote:
> > On Wed, Aug 12, 2015 at 03:09:44PM +0300, Joonas Lahtinen wrote:
> > > Add a comment about reinforcing command order so that
> > &g
On Tue, Aug 11, 2015 at 03:04:17PM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > Either of you opposed to doing it as a follow-on patch? (This failure
> > you speak of was the primary goal for removing it). Initially, I tried
> > to remove it, but we do still se
On Fri, Aug 14, 2015 at 04:51:52PM -0700, Anuj Phogat wrote:
> This change is required by the later patches.
>
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw_misc_state.c| 8
On Fri, Aug 14, 2015 at 04:51:53PM -0700, Anuj Phogat wrote:
> A later patch in this series uses it to compute tile dimensions.
>
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++-
> src/mesa/drivers/dri/i965/brw
On Fri, Aug 14, 2015 at 04:51:54PM -0700, Anuj Phogat wrote:
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 67
> ++-
> src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 5 ++
> 2 files c
On Fri, Aug 14, 2015 at 04:51:55PM -0700, Anuj Phogat wrote:
> It takes care of using the correct tile width if we later use other tiling
> patterns (e.g. Yf) for aux miptree.
>
> Cc: Ben Widawsky
> Signed-off-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/gen8
048...)/4 (in Dwords)."
>
> This patch adds the restriction for X tiling as well.
>
> Cc: Ben Widawsky
> Cc:
> Signed-off-by: Anuj Phogat
I don't think you need to Cc stable because the other tiling modes aren't used,
right? (also, the backport you've
I pushed this because it was annoying me and Neil is on vacation.
On Thu, Aug 13, 2015 at 09:06:39AM +0300, Tapani Pälli wrote:
> Reviewed-by: Tapani Palli
>
> On 08/10/2015 07:31 PM, Neil Roberts wrote:
> >Since 4d7e0fa8c731776 this file is generated by the configure script.
> >---
> > src/gal
On Mon, Jul 13, 2015 at 06:01:14PM +0100, Neil Roberts wrote:
> The edge flag data on Gen6+ is passed through the fixed function hardware as
> an extra attribute. According to the PRM it must be the last valid
> VERTEX_ELEMENT structure. However if the vertex ID is also used then another
> extra el
hese patches and I'd prefer if you held off on merging
them to stable for now (they aren't yet in master).
Thanks.
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
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n is the use of the dummy element - I can't make sense of why
it's needed, but it clearly is.
On Tue, Aug 18, 2015 at 06:27:42PM -0700, Ben Widawsky wrote:
> On Mon, Jul 13, 2015 at 06:01:14PM +0100, Neil Roberts wrote:
> > The edge flag data on Gen6+ is passed through the fixed
related to this patch.
Cc: Chris Wilson
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 7ee3cb6..a2aef8a
On Wed, Aug 26, 2015 at 10:52:58AM -0700, Ben Widawsky wrote:
> Docs suggest this is no longer required starting with Gen8.
>
> Perf (no regressions in n=20)
> OglMultithread 0.67%
> OglTerrainPanInst0.12%
> trex 0.45%
> warsow 0.64%
s the script I used for bisect:
i=0
while [ $i -lt 40 ] ; do
./bin/texsubimage pbo -auto -fbo > /dev/null 2>&1
[[ $? != 0 ]] && echo fail && exit 1
((i++))
done
exit 0
Cc:
Cc: Kenneth Graunke
Cc: Topi Pohjolainen
Reported-by: Mark Janes (jenkins)
Signed-off-
On Thu, Aug 27, 2015 at 10:51:59AM +0300, Pohjolainen, Topi wrote:
> On Wed, Aug 26, 2015 at 03:46:05PM -0700, Ben Widawsky wrote:
> > This reverts commit 1bba29ed403e735ba0bf04ed8aa2e571884fcaaf
> > Author: Topi Pohjolainen
> > Date: Thu Jun 25 14:00:41 2015 +0300
> &
Gen9 changes the meaning of this to coarse LOD quality mode. Although that's a
desirable thing to be setting, it doesn't match the gen8 behavior and this was
unintentional.
This doesn't fix, or regress anything on SKL (AFAICT).
Signed-off-by: Ben Widawsky
---
src/mesa/d
tml
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_defines.h | 16
src/mesa/drivers/dri/i965/gen8_ps_state.c | 8 ++--
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drive
On Thu, Aug 27, 2015 at 11:50:52AM -0700, Ben Widawsky wrote:
Subject should read gen9. Fixed locally
> Gen9 changes the meaning of this to coarse LOD quality mode. Although that's a
> desirable thing to be setting, it doesn't match the gen8 behavior and this was
> unint
On Thu, Aug 27, 2015 at 11:50:51AM -0700, Ben Widawsky wrote:
> As far as I can tell, the behavior is preserved from the previous generations.
> Before we set a single bit to tell the FS whether or not we'll be using an
> input
> coverage mask. Now we have some options which
On Thu, 27 Aug 2015 23:24:26 -0700
Kenneth Graunke wrote:
> On Thursday, August 27, 2015 11:50:52 AM Ben Widawsky wrote:
> > Gen9 changes the meaning of this to coarse LOD quality mode.
> > Although that's a desirable thing to be setting, it doesn't match
> >
On Fri, Aug 28, 2015 at 10:15:30AM +0300, Pohjolainen, Topi wrote:
> On Fri, Aug 28, 2015 at 09:56:43AM +0300, Pohjolainen, Topi wrote:
> > On Thu, Aug 27, 2015 at 10:05:14AM -0700, Ben Widawsky wrote:
> > > On Thu, Aug 27, 2015 at 10:51:59AM +0300, Pohjolainen, Topi wrote:
>
On Mon, Aug 03, 2015 at 11:00:05PM -0700, Jordan Justen wrote:
> brw_upload_cs_push_constants was based on gen6_upload_push_constants.
>
> v2:
> * Add FINISHME comments about more efficient ways to push uniforms
>
> Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
Revi
From: Ben Widawsky
The code already skips doing the depth stall on gen >= 8, and as we
enable new platforms this assertion will fail needlessly. Instead of
changing the caller, make this simple change.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
1 f
On 16-10-04 15:38:52, Lionel Landwerlin wrote:
Embed the xml files into the binary, so aubinator can be used from any
location.
Signed-off-by: Lionel Landwerlin
Cc: Sirisha Gandikota
---
src/intel/Makefile.am | 1 +
src/intel/Makefile.aubinator.am | 36 +++
src/intel/Makef
Reviewed-by: Ben Widawsky
On 16-10-04 08:03:05, Jason Ekstrand wrote:
Reviewed-by: Jason Ekstrand
On Wed, Sep 21, 2016 at 2:42 PM, Nanley Chery wrote:
Use the vertex positions described in the PRMs. This has no effect on
rendering but quiets the simulator warnings seen when the vertices
On 16-10-04 16:03:28, Lionel Landwerlin wrote:
On 04/10/16 16:01, Eero Tamminen wrote:
Hi,
On 04.10.2016 17:38, Lionel Landwerlin wrote:
In conjuction with an intel_aubdump change, you can now look at your
application's output like this :
$ intel_aubdump -c '/path/to/aubinator --gen=hsw' my_g
On 16-10-04 15:38:53, Lionel Landwerlin wrote:
In conjuction with an intel_aubdump change, you can now look at your
application's output like this :
$ intel_aubdump -c '/path/to/aubinator --gen=hsw' my_gl_app
Signed-off-by: Lionel Landwerlin
Cc: Sirisha Gandikota
Cc: Kristian Høgsberg
---
sr
On 16-10-04 09:50:55, Kenneth Graunke wrote:
On Tuesday, October 4, 2016 9:26:39 AM PDT Ben Widawsky wrote:
On 16-10-04 15:38:52, Lionel Landwerlin wrote:
>Embed the xml files into the binary, so aubinator can be used from any
>location.
>
>Signed-off-by: Lionel Landwerlin
All mobile parts (so far) are GT1. The check added extra confusion
because it appeared Broxton was missing when it wasn't. Replace it with
a comment.
Alternatively, I'd be willing to add an is_broxton check.
Cc: Francisco Jerez
Signed-off-by: Ben Widawsky
---
src/intel/common/gen_l
There should be no functional change here because Broxton and CHV are
both gt1. Without this code however, it might seem like broxton support
is missing.
While here, put the gt1 check in front to hopefully short-circuit the
condition for the mobile cases.
Cc: Francisco Jerez
Signed-off-by: Ben
On 16-10-12 14:21:08, Matt Turner wrote:
On Tue, Oct 11, 2016 at 12:26 PM, Topi Pohjolainen
wrote:
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri
I have some OCD...
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index a93228d..e482007 100644
--- a/include/pci_ids
We got a couple for products that exist on ark.intel.com, so let's just
put them in now.
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_
On 16-10-11 22:26:33, Topi Pohjolainen wrote:
And fix a mangled comment while at it.
Signed-off-by: Topi Pohjolainen
CC: Ben Widawsky
CC: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++-
src/mesa/drivers/dri/i965/brw_meta_util.c | 56 +--
src
| image_y >= 32768)
- return false;
-
/* See intel_miptree_blit() for details on the 32k pitch limit. */
if (mt->pitch >= 32768)
return false;
--
2.5.0.400.gff86faf
--
Ben Widawsky, Intel Open Source Technology Center
___
mes
Series is:
Reviewed-by: Ben Widawsky
On 16-10-26 11:29:51, Anuj Phogat wrote:
On Tue, Oct 25, 2016 at 4:36 PM, Ilia Mirkin wrote:
On Tue, Oct 25, 2016 at 7:09 PM, Anuj Phogat wrote:
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_wm.c | 4 ++--
src/mesa/drivers/dri
On 16-11-07 10:22:46, Lionel Landwerlin wrote:
On 07/11/16 10:07, Pohjolainen, Topi wrote:
On Thu, Nov 03, 2016 at 10:39:39AM +, Lionel Landwerlin wrote:
From: Ben Widawsky
libdrm may round up the allocation requested by mesa. As a result, accesses
through the gtt may end up accessing
From: Ben Widawsky
v2:
Fix KBL typo while here
s/bdw/gen
Add the 2x6 config
Cc: "13.0"
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 2 ++
src/intel/common/gen_device_info.c | 44 ++
2 files changed, 46 insertions(+)
di
On 16-11-10 10:20:13, Ben Widawsky wrote:
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index fbc3999..b938332 100644
--- a
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
src/intel/common/gen_device_info.c | 116 +
1 file changed, 40 insertions(+), 76 deletions(-)
diff --git a/src/intel/common/gen_device_info.c
b/src/intel/common/gen_device_info.c
index 3b09072..055fc24
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index fbc3999..b938332 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include
From: Ben Widawsky
Signed-off-by: Ben Widawsky
---
intel/intel_chipset.h | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 514f659..41fc0da 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
On 16-11-15 03:08:22, Kenneth Graunke wrote:
This was missing.
Signed-off-by: Kenneth Graunke
Cc: stable?
Reviewed-by: Ben Widawsky
Would you mind taking a quick look at the cleanup patch I have for defining GEN9
and GEN9_LP feature macros?
---
src/intel/common/gen_device_info.c | 2 ++
1
From: Ben Widawsky
When 1 BO is used for aux data, it needs to point to the correct offset,
which will not be the BOs offset but instead an offset from the BOs
offset. Since today there are always multiple BOs for aux, this doesn't
actually change anything.
Cc: Jason Ekstrand
Signed-o
On 16-11-16 11:25:32, Jason Ekstrand wrote:
On Tue, Nov 15, 2016 at 5:35 PM, Ben Widawsky
wrote:
From: Ben Widawsky
When 1 BO is used for aux data, it needs to point to the correct offset,
which will not be the BOs offset but instead an offset from the BOs
offset. Since today there are
mail.com> wrote:
>
> Originally re-clears where skipped but when lossless compression
> was introduced the re-clears where errorneously enabled also for
> non-compressed fast clears.
> Signed-off-by: Topi Pohjolainen <[2]topi.pohjolai...@intel.com>
>
st that we've cared
about which are a big deal.
I realize that we maybe aren't doing things correctly today, but we don't seem
to have failures AFAIK.
Anyway, I'm just asking us to be thorough.
[snip]
--
Ben Widawsky, Intel Open Source Technology Center
From: Ben Widawsky
I intend to need to get to the devinfo structure, and storing the screen
is an easy way to do that.
It seems to be the consensus that you cannot share an image between
multiple screens.
Scape-goat: Rob Clark
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965
From: Ben Widawsky
Unlike stride, there was no previous offset getter, so it can be right
on the first try.
Signed-off-by: Ben Widawsky
---
src/gbm/backends/dri/gbm_dri.c | 27 +++
src/gbm/gbm-symbols-check | 1 +
src/gbm/main/gbm.c | 15
From: Ben Widawsky
Previously our aux buffers (MCS, and HiZ) never had an offset because
they were in their own buffer object. When using the CCS lossless
compression feature, it's desirable to store the data at an offset from
the main framebuffer, ie. share a buffer object. This patch
From: Ben Widawsky
Other things are out of order, but I need to add a getter so I'm just
fixing those.
This helps people adding to GBM know where the right place to put things
is.
Signed-off-by: Ben Widawsky
---
src/gbm/main/gbm.c | 22 +++---
1 file changed, 11 inser
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