s for GT4
parts.
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 33 ++---
1 file changed, 18 insertions(+), 15 deletions(-)
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 626064a..2747dc5 100644
--- a/include/pc
I left the function to obtain the revision because it is, and will continue to
be useful in the future. I'd rather not have to dig it up every time we need it.
Comments left at the implementation to say as much.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_device_info.c
On Fri, Oct 23, 2015 at 02:38:39PM -0700, Ben Widawsky wrote:
> I left the function to obtain the revision because it is, and will continue to
> be useful in the future. I'd rather not have to dig it up every time we need
> it.
> Comments left at the implementation to say a
On Fri, Oct 23, 2015 at 06:19:02PM -0700, Vivek Kasireddy wrote:
> On Thu, 22 Oct 2015 21:12:02 -0700
> Ben Widawsky wrote:
>
> > On Thu, Oct 22, 2015 at 06:44:53PM -0700, Vivek Kasireddy wrote:
> > > On newer hardware platforms that support rotation, if the gbm
>
(p, BRW_ALIGN_16);
> }
> brw_pop_insn_state(p);
> }
I'm assuming this is because the correct access mode is always set up before
generating the assembly (probably wouldn't hurt to have added that to the commit
message for naive people like myself)?
If so:
Reviewed-by
the wm thread count to support GT4.
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Ben Widawsky
---
include/pci_ids/i965_pci_ids.h | 4
src/mesa/drivers/dri/i965/brw_device_info.c | 6 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/include/pci_ids
On Fri, Oct 30, 2015 at 01:38:47PM -0700, Ian Romanick wrote:
> On 10/29/2015 05:30 PM, Ben Widawsky wrote:
> > Like other gen8+ hardware, the hardware automatically scales up thread
> > counts
> > and URB sizes, so there is no need to do anything but add the PCI IDs.
>
nkins)
References: https://www.opengl.org/registry/specs/ARB/texture_view.txt
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src
On Mon, Nov 02, 2015 at 12:05:32PM -0800, Ben Widawsky wrote:
> It is legal to have a texture view of a single layer from a 2D array texture;
> you can sample from it, or render to it. Intel hardware needs to be made aware
> when it is using a 2d array surface in the surface state. Th
lla: https://bugs.freedesktop.org/show_bug.cgi?id=92609
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surfa
iven that I usually opt for fewer patches.
I've modified this locally to summarize the above. I haven't read your review
comments for the patches after this yet. It's likely that you noticed this, and
we can continue the discussion there.
> On Tue 13 Oct 2015, Ben Widawsky wrote:
On Fri, Oct 16, 2015 at 04:05:22PM -0700, Chad Versace wrote:
> On Tue 13 Oct 2015, Ben Widawsky wrote:
> > Initially I had this planned as a patch to be squashed in to the enabling
> > patch
> > because there is no point enabling fast clears without this. However, Chad
>
On Tue, Oct 13, 2015 at 09:14:29PM -0700, Matt Turner wrote:
> On Tue, Oct 13, 2015 at 9:12 PM, Matt Turner wrote:
> > On Tue, Oct 13, 2015 at 8:50 PM, Ben Widawsky
> > wrote:
> >> The impetus for this patch comes from a seemingly benign statement within
> >>
On Wed, Nov 04, 2015 at 06:11:09PM +0100, Neil Roberts wrote:
> Neil Roberts writes:
>
> > Normally this doesn't matter because fast color clears are only
> > available on Gen7+ and for that hardware we also always set the
> > texture swizzle to force the missing components to zero or one.
>
> L
The comment in the code details the restriction. Thanks to Ken for having a very
helpful conversation with me, and spotting the blurb in the link I sent him :P.
There are still stability problems for me on GT4, but this definitely helps with
some of the failures.
Cc: Kenneth Graunke
Cc: Jordan J
On Fri, Nov 06, 2015 at 07:29:18PM -0800, Kenneth Graunke wrote:
> On Friday, November 06, 2015 06:12:27 PM Ben Widawsky wrote:
> > The comment in the code details the restriction. Thanks to Ken for having a
> > very
> > helpful conversation with me, and spotting the blurb i
On Mon, Nov 09, 2015 at 11:50:25AM -0800, Kenneth Graunke wrote:
> On Saturday, November 07, 2015 08:40:51 AM Ben Widawsky wrote:
> > On Fri, Nov 06, 2015 at 07:29:18PM -0800, Kenneth Graunke wrote:
> > > On Friday, November 06, 2015 06:12:27 PM Ben Widawsky wrote:
> > >
On Mon, Nov 09, 2015 at 11:59:43PM -0800, Kenneth Graunke wrote:
> We basically just need to uncomment Ben's code.
>
> Signed-off-by: Kenneth Graunke
> ---
> src/mesa/drivers/dri/i965/gen6_queryobj.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drive
There is one thing I need a response on at the very bottom, the rest will be
addressed in v2.
Thanks.
On Mon, Nov 09, 2015 at 11:33:17AM -0800, Chad Versace wrote:
> On Tue 03 Nov 2015, Ben Widawsky wrote:
> > On Fri, Oct 16, 2015 at 04:05:22PM -0700, Chad Versace wrote:
> > >
On Wed, Oct 14, 2015 at 08:16:54AM -0700, Ben Widawsky wrote:
> On Wed, Oct 14, 2015 at 11:52:03AM +0200, Neil Roberts wrote:
> > This patch doesn't look right. See this sentence in “Render Target Fast
> > Clear”:
> >
> > “The pixel shader kernel requires no att
branch may be found here:
http://cgit.freedesktop.org/~bwidawsk/mesa/log/?h=skl-fast-clear
NOTE: These patches "regress"
piglit.spec.arb_shader_image_load_store.execution.load-from-cleared-image
because of this bug: https://bugs.freedesktop.org/show_bug.cgi?id=92849
Cc: Chad Versace
Be
)
Use the helper function and don't increase the context size - this is mostly
implemented in the patch just before this (Chad, Neil)
Remove an "invalid" assert (Chad)
Fix assertion to check num_samples > 1, instead of num_samples (Chad)
Cc: Chad Versace
Cc: Neil Roberts
Signed-
This reverts commit dcd59a9e322edeea74187bcad65a8e56c0bfaaa2.
Reviewed-by: Neil Roberts
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8
1 file changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
inde
nrelated to enabling this on GEN9, it becomes somewhat tricky to implement
because of the fact that surface format support diminishes. You'd probably want
another column to cleanly implement it.
Requested-by: Chad Versace
Requested-by: Neil Roberts
Signed-off-by: Ben Widawsky
---
ight = 4;
+ if (brw->gen >= 9)
+ *height = 2;
+ else
+ *height = 4;
v2: Add braces for the multiline (Matt + Chad)
Comment updates (requested by Chad)
Modified commit message
Commit message from Chad explaining the MCS height change (Chad)
Cc: Chad Versace
Sign
This reverts commit 8a0c85b25853decb4a110b6d36d79c4f095d437b.
It's not a strict revert because I don't want to bring back the gen < 9 check at
this point in time.
Reviewed-by: Neil Roberts
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 5 -
1 file changed, 5 deletions(-)
diff --git
SKL supports the ability to do fast clears and resolves of 32b RGBA as both
integer and floats. This patch only enables float color clears because we
haven't yet enabled integer color clears, (HW support for that was added in
BDW).
Two formats are explicitly disabled because they fail piglit tests
mt (Chad)
Cc: Chad Versace
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 94 +
1 file changed, 81 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
b/src/mesa/drivers/dri/i965
This subject used to say Add lossless compression to surface format TO table
somehow, "to" got dropped. It's fixed locally.
On Wed, Nov 11, 2015 at 02:06:16PM -0800, Ben Widawsky wrote:
> Background: Prior to Skylake and since Ivybridge Intel hardware has had the
>
On Wed, Nov 11, 2015 at 02:10:57PM -0800, Ben Widawsky wrote:
> This subject used to say Add lossless compression to surface format TO table
>
> somehow, "to" got dropped. It's fixed locally.
>
Ignore this, subject looks fine to
On Thu, Nov 12, 2015 at 11:39:25AM +0100, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > Two formats are explicitly disabled because they fail piglit tests,
> > LUMINANCE16F and INTENSITY16F. There is some question about the
> > validity of sampling from these surfac
---
Here is one proposal to fix the issue. I noticed that only formats without alpha
were failing. This sucks for RGBX formats (which technically aren't fast
clearable based on the surface format). The hunk for moving the format should
happen regardless of this patch.
Neil has another patch which
patch if you want, or of course if you prefer to keep your patch as
> it is it's up to you.
Thanks a lot, I will squash it in - and sorry again about ignoring your
feedback.
>
> Regards,
> - Neil
>
> Ben Widawsky writes:
[snip]
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T_CLEAR_STATE_CLEAR, the
Seems like a good patch to me. It would probably be nice to track down a good
spec reference if you manage to find one. I know I've seen such reference in SKL
docs (which aren't SKL specific) - but I am having trouble finding it in PRMs.
My VPN is broken, so I can't look at SKL docs right now.
With the explanation of why the luminance alpha channel isn't 1 (I also claim
incompotence on the GL_LUMINANCE_ALPHA format):
Reviewed-by: Ben Widawsky
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> +
>if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS)
> clear_type = REP_CLEAR;
>
(Perhaps "Disable fast clears..." is a misleading title because it
doesn't really disable them. A note that thi
On Mon, Feb 02, 2015 at 11:37:26PM -0500, Ilia Mirkin wrote:
> On Mon, Dec 8, 2014 at 9:50 PM, Ben Widawsky wrote:
> > Thanks. All the requests look good, and I'll post it in v3.
>
> What happened to this patch? It was pretty close... should be easy to
> add gallium suppo
s in the future.
>
> Signed-off-by: Kenneth Graunke
Both are:
Reviewed-by: Ben Widawsky
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On Wed, Jan 14, 2015 at 10:42:01AM -0800, Jason Ekstrand wrote:
> On Tue, Jan 13, 2015 at 11:37 PM, Ben Widawsky
> wrote:
>
> > The blit engine is limited to 32Kx32K transfer. In cases where we have to
> > fall
> > back to the blitter, and when trying to blit a slic
On Wed, Jan 14, 2015 at 10:34:52AM -0800, Jason Ekstrand wrote:
> On Tue, Jan 13, 2015 at 11:37 PM, Ben Widawsky
> wrote:
>
> > This patch will use a new calculation to determine if a surface can be
> > blitted
> > from or to. Previously, the "total_height"
Instead of iterating in reverse through blocks and
insts, since the last block/inst is the only thing which can benefit.
Rebased on top of Ken's patching modifying is_last_send
Cc: Kenneth Graunke
Cc: Jason Ekstrand
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp
ray.vert
glslparsertest/glsl2/condition-07.vert
spec/glsl-es-3.00/compiler/uniform_block/interface-name-field-clashes-with-variable.vert
Cc: Neil Roberts
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/
On Wed, Feb 11, 2015 at 05:08:33AM -0800, Kenneth Graunke wrote:
> On Tuesday, February 10, 2015 05:22:45 PM Ben Widawsky wrote:
> > Since we can be in this code with SIMD4x2, the execsize will be 4, and so
> > the
> > register width must be <= 4. If you use a vec8, t
From: Jordan Justen
Signed-off-by: Jordan Justen
Reviewed-by: Ben Widawsky
---
src/mesa/main/context.h | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
index d902ea7..69389ae 100644
--- a/src/mesa/main/context.h
+++ b/src/mesa
since we missed 10.5 window
- Moved compute shader stuff into the switch statement (Jordan)
Cc: Ian Romanick
Cc: Ilia Mirkin
Signed-off-by: Ben Widawsky
i965/cs: Add CS pipeline_stats support (squash)
Signed-off-by: Jordan Justen
---
docs/relnotes/10.6.0.html| 2 +-
Brian Paul)
Add checks for desktop gl (Ilia)
Fail for any callers for now (Ilia)
Update QueryCounterBits for new tokens (Ilia)
Jordan: Use _mesa_has_compute_shaders
Cc: Jordan Justen
Cc: Ilia Mirkin
Signed-off-by: Ben Widawsky
---
.../glapi/gen/ARB_pipeline_statistics_query.xml| 24 ++
t;, ip++);
> - dump_instruction(inst, file);
> + if (cfg) {
> + int ip = 0;
> + foreach_block_and_inst(block, backend_instruction, inst, cfg) {
> + fprintf(file, "%4d: ", ip++);
> + dump_instruction(inst
derived simple as all 1's.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cp
On Mon, Feb 16, 2015 at 09:24:34AM -0800, Jason Ekstrand wrote:
> On Feb 16, 2015 7:46 AM, "Francisco Jerez" wrote:
> >
> > Jason Ekstrand writes:
> >
> > > On Feb 15, 2015 11:55 PM, "Ben Widawsky"
> > > wrote:
> > >>
> &
On Tue, Feb 17, 2015 at 11:37:44AM -0800, Ian Romanick wrote:
> On 02/13/2015 11:02 PM, Ben Widawsky wrote:
> > From: Jordan Justen
> >
> > Signed-off-by: Jordan Justen
> > Reviewed-by: Ben Widawsky
> > ---
> > src/mesa/main/context.h | 11 +++
On Tue, Feb 17, 2015 at 11:41:01AM -0800, Ian Romanick wrote:
> On 02/13/2015 11:02 PM, Ben Widawsky wrote:
> > This was originally part of a single patch which added the extension, and
> > implemented it for i965 classic. For information about the evolution of the
> >
since we missed 10.5 window
- Moved compute shader stuff into the switch statement (Jordan)
- Jordan: Add compute shader support
v5:
- Fixed relnote styles (Ilia)
Cc: Ian Romanick
Cc: Ilia Mirkin
Signed-off-by: Ben Widawsky
---
docs/relnotes/10.6.0.html| 4 +
dn't hurt to throw this same optimization at the FS for
cases where we have to fall back though.
Cc: Kenneth Graunke
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
I have no had time to benchmark this very much, nor run piglit on it. I am just
sending it out before it bitrots too m
On Tue, Feb 17, 2015 at 04:59:37PM -0800, Matt Turner wrote:
> On Tue, Feb 17, 2015 at 4:44 PM, Ben Widawsky
> wrote:
> > With scalar VS, it so happens that many vertex shaders will line up in a
> > such a
> > way that two SIMD8 instructions can be collapsed into 1 SIMD
s.
>
> I think the previous change will fix cases that write atomics, such as
> atomicCounterIncrement, and this change will fix cases than only read
> atomics, such as atomicCounter.
>
> Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
> Cc: Francisco J
On Tue, Feb 17, 2015 at 06:14:14PM -0800, Ian Romanick wrote:
> On 02/17/2015 04:21 PM, Ben Widawsky wrote:
> > On Tue, Feb 17, 2015 at 11:41:01AM -0800, Ian Romanick wrote:
> >> On 02/13/2015 11:02 PM, Ben Widawsky wrote:
> >>> This was originally part of a single p
about the Cc 10.5 only because I couldn't find wins on
BSW, and that makes me worry that we missed something - since I was really
expecting to see something. I'll defer to you on that however.
The idea makes sense to me.
Acked-by: Ben Widawsky
[snip]
__
On Tue, Feb 17, 2015 at 02:03:36PM +, Neil Roberts wrote:
> According to the bspec since Skylake the qpitch value in the surface
> formats should be measured in pixels rather than rows for 1D textures.
> ---
> src/mesa/drivers/dri/i965/gen8_surface_state.c | 30
> +++---
>
On Wed, Feb 18, 2015 at 07:13:54PM +, Neil Roberts wrote:
> Ben Widawsky writes:
>
> > I promise to look at this again in more detail tomorrow when I am more
> > awake, but meanwhile, I'd be very much in favor of just setting
> > mt->qpith for all miptree layo
nnels may not end
> up issuing the atomic operation.
>
> Signed-off-by: Jordan Justen
> Cc: Ben Widawsky
> Cc: Francisco Jerez
Just add to the commit message that this is needed specifically because compute
is invoked as SIMD16 (and perhaps reference the other commits?) and it'
zilla: https://bugs.freedesktop.org/show_bug.cgi?id=89118
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88999
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
or us. This patch implements the latter approach.
>
> Fixes the following piglit test:
> bin/arb_pipeline_statistics_query-geom -auto
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210
> Tested-by: Mark Janes
Reviewed-by: Ben Widawsky
On Thu, Feb 19, 2015 at 11:25:56PM -0800, Jordan Justen wrote:
> On 2015-02-19 21:40:37, Ben Widawsky wrote:
> > On Thu, Feb 19, 2015 at 03:42:05PM -0800, Jordan Justen wrote:
> > > For fragment programs, we pull this mask from the payload header. The same
> > > mas
On Fri, Feb 20, 2015 at 03:34:21AM -0800, Kenneth Graunke wrote:
> On Thursday, February 19, 2015 10:48:08 PM Ben Widawsky wrote:
> > When under dispatch_width=16 the previous code would allocate 2 registers
> > for
> > the payload when only one is needed. This manifested i
x27;s
> still really difficult to see what's going on.
Have you already considered that this shortcircuits the next block which
according to the comment improves the ability to fold constants, or do we end up
through here again later? (I'm sure you're aware I know little about t
On Wed, Feb 11, 2015 at 02:54:51PM -0800, Matt Turner wrote:
> total instructions in shared programs: 5932832 -> 5932736 (-0.00%)
> instructions in affected programs: 8184 -> 8088 (-1.17%)
> helped:52
> HURT: 14
> GAINED:
On Sun, Feb 08, 2015 at 02:48:02PM -0800, Matt Turner wrote:
> On Sun, Feb 8, 2015 at 1:59 PM, Ben Widawsky
> wrote:
> > Certain platforms support the ability to sample from a texture, and write
> > it out
> > to the file RT - thus saving a costly send instructions (and
n >= 9)
> + brw_miptree_layout_texture_array(brw, mt);
> + else
> + brw_miptree_layout_texture_3d(brw, mt);
>break;
>
> case GL_TEXTURE_1D_ARRAY:
Reviewed-by: Ben Widawsky
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On Mon, Feb 23, 2015 at 09:38:42AM -0800, Matt Turner wrote:
> On Sun, Feb 22, 2015 at 2:23 PM, Ben Widawsky wrote:
> > On Wed, Feb 11, 2015 at 02:54:51PM -0800, Matt Turner wrote:
> >> total instructions in shared programs: 5932832 -> 5932736 (-0.00%)
> >> ins
From: Kristian Høgsberg
v2 by Ben:
Rebase with conflict resolution
Add the SKL scaling factors
Squashed in i965/skl: Dont zero surf[12]. The patch can't work properly without
that, so there's no point in a separate patch.
Signed-off-by: Kristian Høgsberg
Reviewed-by: Ben Widawsky
ests at it:
tests/fast_color_clear/all-colors.shader_test
tests/fast_color_clear/non-redundant-clear.shader_test
tests/fast_color_clear/redundant-clear.shader_test
tests/fast_color_clear/fast-slow-clear-interaction.shader_test
Cc: Kristian Høgsberg
Signed-off-by: Ben Widawsky
---
src/gallium/d
On Thu, Feb 26, 2015 at 03:42:53PM -0800, Ben Widawsky wrote:
> Keep this as a separate patch for review, but I will squash it with the
> previous
> patch before pushing.
>
> We don't support 16x MSAA yet, but I entered it in here while I was at the
> table.
>
&g
Recomendation [sic] is to set this field to 1 always. Programming it to default
value of 0, may have -ve impact on performance for MSAA WLs.
Another don't suck bit which needs to get set.
Totally untested.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_misc_state.c
ce at initialization and make sure the pma workaround doesn't set the mask bit
(which it doesn't).
Move LRI to init gpu state (Ken)
Add a comment.
... still untested.
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_state_upload.c | 10 ++
src/m
while I was trying to implement workarounds and spotted
some things called, "flush" which should have been called "invalidate."
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/brw_program.c | 10 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2
may exist in the i915
driver as well.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index db2f345..
nce back to back CS stalls probably have
little measurable impact anyway - but it would be less commands.
v2: Rebased on master
Updated commit message
Filled picked a different PIPE_CONTROL flag
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 12 +++
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index b0ebec7..e405918 100644
--- a/src/mesa/drivers
On Fri, Feb 27, 2015 at 10:22:10AM -0800, Ben Widawsky wrote:
> From the comments in the code:
>
>Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
>sending it off.
>
> This fixes a possible, unlikely infinite recursion in our batch f
v2: Sent out the wrong patch original. This patches switches the order of
flushes, doing the generic flush before the CC_STATE, and the required
workaround flush afterwards
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 17 +
1 file changed, 17
On Fri, Feb 27, 2015 at 10:22:10AM -0800, Ben Widawsky wrote:
> From the comments in the code:
>
>Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END and
>sending it off.
>
> This fixes a possible, unlikely infinite recursion in our batch f
uot;This field must be
set to an integer multiple of the Surface Horizontal Alignment."
Note, I don't know anything about compressed textures and what the block widths
can be, but just doing the math, if block size > 16 and not a multiple of 16,
this constraint will not hold.
maybe:
assert
On Sat, Feb 28, 2015 at 12:31:59AM -0800, Kenneth Graunke wrote:
> On Friday, February 27, 2015 10:22:10 AM Ben Widawsky wrote:
> > From the comments in the code:
> >
> >Called from intel_batchbuffer_flush before emitting MI_BATCHBUFFER_END
> > and
> >se
On Sat, Feb 28, 2015 at 12:27:05AM -0800, Kenneth Graunke wrote:
> On Friday, February 27, 2015 10:22:11 AM Ben Widawsky wrote:
> > Signed-off-by: Ben Widawsky
> > ---
> > src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16
> > 1 file changed, 16
nd the required
workaround flush afterwards
v3: Only perform workaround for render ring
Add text to the BATCH_RESERVE comments
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 17 +
src/mesa/drivers/dri/i965/intel_batchbuffer
> break if you used that functionality. (Thankfully, no one does...)
>
> Signed-off-by: Kenneth Graunke
I have my IRC reviewed-by in case you forgot:
Reviewed-by: Ben Widawsky
Maybe a comment about how the existing 146 seems wrong?
> ---
> src/mesa/drivers/dri/i965/intel_batchb
GL_ARB_texture_float -auto -fbo
Cc: Ian Romanick
Cc: Brian Paul
Cc: Eric Anholt
Reported-by: Mark Janes (Jenkins)
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/common/meta.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index
allocation after the early return block (v2)
Cc: Ian Romanick
Cc: Brian Paul
Cc: Eric Anholt
Cc: Kenneth Graunke
Signed-off-by: Ben Widawsky
---
Thanks Ken. I wasn't sure if this path was common or not, and I had opted for
the standard, define variables at the top, style. If it occurs more
>total_width, mt->total_height, mt->cpp);
> +
> + /* On Gen9+ the alignment values are expressed in multiples of the block
> +* size
> +*/
> + if (brw->gen >= 9) {
> + unsigned int i, j;
> + _mesa_get_format_block_size(mt->format, &i, &a
{
> + switch (mt->msaa_layout) {
> + case INTEL_MSAA_LAYOUT_NONE:
> + case INTEL_MSAA_LAYOUT_IMS:
> + mt->array_layout = ALL_LOD_IN_EACH_SLICE;
> + break;
> + case INTEL_MSAA_LAYOUT_UMS:
> + case INTEL
e busy.
>
> Signed-off-by: Kenneth Graunke
Sorry I let this slip. I actually thought it was merged, and screwed up the
patchwork state.
This is both:
Tested-by: Ben Widawsky &&
Reviewed-by: Ben Widawsky
My only nit is that I do already have the fix for this. Not sure if we want to
ng intermittent GL_OUT_OF_MEMORY errors which I was too lazy to
track down since I assumed it wasn't my fault. Well, I finally tracked it down
and fixed it:
commit 7aba4ab1f355ea1a5870b3deb4b295565132dfc5
Author: Ben Widawsky
Date: Fri Mar 6 17:31:00 2015 -0800
meta: Plug memory leak
Ben Widaws
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c| 11 ++-
src/mesa/drivers/dri/i965/intel_blit.h| 3 +++
src/mesa/drivers/dri/i965/intel_copy_image.c | 7 ---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +
4 files changed, 18
esn't change all places which check blitter requirements. I
will be adding those as a separate patch(es) since the original series, which
was well tested, did not include those.
This was requested by Jordan and Jason.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_b
work.freedesktop.org/patch/38909/
Cc: Jordan Justen
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 55 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 21 ++
2 files changed, 52 insertions(+), 24 deletions(-)
diff --git a/src/m
:
> Destination Y2 Coordinate (Bottom)
> 16 bit signed number.
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 8 ++--
src/mesa/drivers/dri/i965/intel_copy_image.c | 8 ++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dr
parameter from the y adjusting function (~Jason)
Add assert that adjusted y offset is within bounds
Renamed and moved the helper functions "public" in intel_blit.h
v3.1:
Fixed assertion fail from v3 (Jordan)
Remove conditional y adjusted calculation, replace with comment (Jordan + Jason)
i965: Fix condition to use Y tiling in blitter in intel_miptree_create()
Cc: Kenneth Graunke
Cc: Chad Versace
Cc: Anuj Phogat
Signed-off-by: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/dr
On 17-01-25 21:05:15, Topi Pohjolainen Topi Pohjolainen wrote:
On Wed, Jan 25, 2017 at 09:01:56PM +0200, Pohjolainen, Topi wrote:
On Mon, Jan 23, 2017 at 10:21:40PM -0800, Ben Widawsky wrote:
> Previously our aux buffers (MCS, and HiZ) never had an offset because
> they were in their own
On 17-02-02 13:27:05, Jason Ekstrand wrote:
This improves the performance of Dota 2 on my Sky Lake Skull Canyon
machine by about 2-3%.
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_private.h | 1 +
src/intel/vulkan/gen8_cmd_buffer.c | 157 -
src
On 17-01-31 11:33:39, Jason Ekstrand wrote:
On Mon, Jan 23, 2017 at 10:19 PM, Ben Widawsky wrote:
v2: Preserve legacy behavior when plane is 0 (Jason Ekstrand)
EINVAL when input plane is greater than total planes (Jason Ekstrand)
Don't leak the image after fromPlanar (Daniel)
Move bo-&
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