[Mesa-dev] [PATCH 2/2] i965/skl: [SQUASH] Update the MCS buffer scale sizes

[Ben Widawsky]

Keep this as a separate patch for review, but I will squash it with the previous
patch before pushing.

We don't support 16x MSAA yet, but I entered it in here while I was at the
table.

I'm having trouble getting through a piglit run on SKL at the moment, so I just
few a threw small tests at it:

tests/fast_color_clear/all-colors.shader_test
tests/fast_color_clear/non-redundant-clear.shader_test
tests/fast_color_clear/redundant-clear.shader_test
tests/fast_color_clear/fast-slow-clear-interaction.shader_test

Cc: Kristian Høgsberg <k...@bitplanet.net>
Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
 src/gallium/drivers/ilo/ilo_layout.c            |  5 ++++-
 src/mesa/drivers/dri/i965/brw_meta_fast_clear.c |  2 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c   | 11 +++++++++--
 3 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/ilo/ilo_layout.c 
b/src/gallium/drivers/ilo/ilo_layout.c
index 0b639b2..c2c8ec5 100644
--- a/src/gallium/drivers/ilo/ilo_layout.c
+++ b/src/gallium/drivers/ilo/ilo_layout.c
@@ -1257,7 +1257,10 @@ layout_calculate_mcs_size(struct ilo_layout *layout,
          break;
       case INTEL_TILING_Y:
          downscale_x = 32 / layout->block_size;
-         downscale_y = 4;
+         if (brw->gen >= 9)
+            downscale_y = 2;
+         else
+            downscale_y = 4;
          break;
       default:
          assert(!"unsupported tiling mode");
diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c 
b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index c4d4b68..f487e97 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -289,6 +289,8 @@ get_fast_clear_rect(struct brw_context *brw, struct 
gl_framebuffer *fb,
       case 8:
          x_scaledown = 2;
          break;
+      case 16:
+         x_scaledown = 1;
       default:
          unreachable("Unexpected sample count for fast clear");
       }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 36c3b26..75ce2b9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -138,10 +138,17 @@ intel_get_non_msrt_mcs_alignment(struct brw_context *brw,
       unreachable("Non-MSRT MCS requires X or Y tiling");
       /* In release builds, fall through */
    case I915_TILING_Y:
-      *width_px = 32 / mt->cpp;
-      *height = 4;
+      if (brw->gen >= 9) {
+         const int scale_factor = 16 / mt->cpp;
+         *width_px = 128 / scale_factor;
+         *height = 64;
+      } else {
+         *width_px = 32 / mt->cpp;
+         *height = 4;
+      }
       break;
    case I915_TILING_X:
+      assert(brw->gen < 9);
       *width_px = 64 / mt->cpp;
       *height = 2;
    }
-- 
2.3.0

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