Reviewed-by: Bas Nieuwenhuizen
On Thu, Jul 27, 2017 at 5:59 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> On SI this was causing a hang in
> dEQP-VK.pipeline.render_to_image.core.2d_array.mipmap.r16g16_sint_s8_uint
>
> This was due to not handling the tile mode index for de
n some APU situations the reported visible size can be larger than
VRAM size. This properly clamps the value.
Surprisingly both CTS and spec seem to allow a heap type with size 0,
so this seemed like the easiest option to me.
Signed-off-by: Bas Nieuwenhuizen
Fixes: 4ae84efbc5c "radv: Use
Signed-off-by: Bas Nieuwenhuizen
Fixes: 601093f95dd "xmlconfig: move into src/util"
Cc: Nicolai Hähnle
---
src/gallium/targets/d3dadapter9/Makefile.am | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/targets/d3dadapter9/Makefile.am
b/src/gallium/targets/d3dadapter9/M
On Tue, Aug 1, 2017 at 12:32 AM, Jordan Justen
wrote:
> To get the extension list:
>
> $ git grep -hE "extension name=\"VK_(EXT|KHR|KHX)" src/vulkan/registry/vk.xml
> | \
> grep -v disabled | awk '{print $2}' | sed -E 's/(name=)?"//g' | sort
>
> To find anv(il) and radv supported extensions:
>
On Tue, Aug 1, 2017 at 3:50 AM, Dave Airlie wrote:
> On 1 August 2017 at 09:40, Marek Olšák wrote:
>> Hi,
>>
>> This might slightly increase MRT performance. You need the amdgpu
>> kernel driver if you want it for SI and CI.
>>
>> I've fixed a few of issues with the original code, enabled it for
LLVM complained about passing an i32 to a float clamp.
Signed-off-by: Bas Nieuwenhuizen
Fixes: 0f9e32519bb "ac/nir: clamp shadow texture comparison value on VI"
---
src/amd/common/ac_nir_to_llvm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/
On Tue, Aug 1, 2017 at 1:27 AM, Jordan Justen wrote:
> On 2017-07-31 16:08:51, Bas Nieuwenhuizen wrote:
>> On Tue, Aug 1, 2017 at 12:32 AM, Jordan Justen
>> > +Vulkan 1.0 -- all DONE: anv
>>
>> So while we don't have conformance, we have at several times had l
the number of buffers in that slab.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 15
src/amd/vulkan/radv_device.c | 5 +++
src/amd/vulkan/radv_pipeline.c | 67 +++-
src/amd/vulkan/radv_pipeline_cache.c | 7
Acked-by: Bas Nieuwenhuizen
On Wed, Aug 2, 2017 at 7:57 PM, Jason Ekstrand wrote:
> lgtm
>
> On Wed, Aug 2, 2017 at 10:51 AM, Jordan Justen
> wrote:
>>
>> To get the extension list:
>>
>> $ git grep -hE "extension name=\"VK_KHR" src/vul
On Fri, Aug 4, 2017 at 12:26 AM, Marek Olšák wrote:
> Hi Alex,
>
> Which game uses texturing from MSAA depth buffers?
They don't necessarily have to do that, radv could also be doing some
superfluous layout transitions that might mess the texture up due to
not taking the samples into account.
-
Reviewed-by: Bas Nieuwenhuizen
On Fri, Aug 4, 2017 at 4:51 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This is a bug in the app, but I'd rather avoid hanging the GPU,
> esp if someone is running in validation and it takes out their
> development environment.
>
>
It justs works with the fragment shader resolve, so no need to do
a custom conversion. In fact with SRGB dest, it actually gives
wrong results.
Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
---
src/amd/vulkan/radv_meta.c| 46 ---
The argument here is a bitmask, so the old code selected .xy, which
got silently truncated to .x when constructing the vec4 from components,
instead of using .w.
Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
---
src/amd/vulkan/radv_meta_resolve_cs.c | 2 +-
1 file
These seem to store very bogus results. Luckily there is some code
that converts srgb->linear already, so just making the descriptor
format UNORM should work.
Fixes: 588185eb6b7 "radv/meta: add srgb conversion to end of resolve shader."
---
src/amd/vulkan/radv_meta_resolve_cs.c | 2 +-
src/amd/v
Reviewed-by: Bas Nieuwenhuizen
On Fri, Aug 4, 2017 at 7:46 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> When Marek enabled mipmapped swizzle, radv didn't
> have the code in place to handle it. This fixes the
> regression.
>
> I'll look more into GFX9 once I h
Reviewed-by: Bas Nieuwenhuizen
On Fri, Aug 4, 2017 at 7:55 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This mirrors what Marek has done for radeonsi, and uses
> a separate counter to handle the fmask surface for MSAA
> MRTs.
>
> Signed-off-by: Dave Airlie
&g
cb->cb_color_attrib |=
> S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
only set it for SI? AFAICS this code is not SI only, but the radeonsi
workaround is.
With that fixed:
Reviewed-by: Bas Nieuwenhuizen
> + }
> + }
>
> if (iview->ima
On Mon, Aug 7, 2017 at 9:14 AM, Dave Airlie wrote:
> On 7 August 2017 at 17:05, Bas Nieuwenhuizen wrote:
>> On Mon, Aug 7, 2017 at 8:42 AM, Dave Airlie wrote:
>>> From: Dave Airlie
>>>
>>> This ports the workaround from radeonsi, that was missing in radv
Also adds an assert because you never know how the winsys changes, and
multiprocess format differences are annoying.
Fixes: 1e696b962b7 "radv: add separate fmask tile swizzle counter."
---
src/amd/vulkan/radv_image.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/amd/
pushed, thanks.
On Thu, Aug 3, 2017 at 4:32 PM, Alex Smith wrote:
> Need to take the sample count into account in the depth decompress and
> resummarize pipelines and render pass.
>
> Fixes: f4e499ec791 ("radv: add initial non-conformant radv vulkan driver")
> Signed-off-by: Alex Smith
> Cc: "17
On Mon, Aug 7, 2017 at 11:51 PM, Ilia Mirkin wrote:
> On Mon, Aug 7, 2017 at 5:37 PM, Bas Nieuwenhuizen
> wrote:
>> Also adds an assert because you never know how the winsys changes, and
>> multiprocess format differences are annoying.
>>
>> Fixes: 1e696b962b7
This patch is
Reviewed-by: Bas Nieuwenhuizen
On Tue, Aug 8, 2017 at 3:45 AM, Connor Abbott wrote:
> From: Connor Abbott
>
> The .f32 was already getting added by emit_intrin_2f_param(). Noticed
> when enabling LLVM module verification.
> ---
> src/amd/common/ac_nir_to_ll
Update:
"Clarify that dedicated allocations do not allow aliasing in the
flink:vkBindBufferMemory and flink:vkBindImageMemory valid usage
statements."
Which is a noop in driver support.
---
src/amd/vulkan/radv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/
---
src/compiler/spirv/vtn_variables.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv/vtn_variables.c
index 4432e72e54a..599b9b11a59 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn
Reviewed-by: Dave Airlie
---
include/vulkan/vulkan.h| 11 ---
src/vulkan/registry/vk.xml | 42 +++---
2 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/include/vulkan/vulkan.h b/include/vulkan/vulkan.h
index 3a74f5e3c87..23a92889ac5 10
Update:
"Clarify that dedicated allocations do not allow aliasing in the
flink:vkBindBufferMemory and flink:vkBindImageMemory valid usage
statements."
Which is a noop in driver support.
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
We were using it internally already.
v2: Add support for the spirv capability.
---
src/amd/vulkan/radv_device.c | 4
src/amd/vulkan/radv_entrypoints_gen.py | 1 +
src/amd/vulkan/radv_pipeline.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/src/amd/vulkan/radv_device
Reviewed-by: Dave Airlie
---
src/compiler/spirv/vtn_variables.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/compiler/spirv/vtn_variables.c
b/src/compiler/spirv/vtn_variables.c
index 4432e72e54a..599b9b11a59 100644
--- a/src/compiler/spirv/vtn_variables.c
++
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 958ae6e361e..ffa7e430b2b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b
Moves from accurate divides to rcp and rsq. No new CTS failures.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 514c9e9ca35
Results in faster code than the lowering by LLVM.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_pipeline.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 8e71d59fae7..5046c9f6b36 100644
--- a/src/amd/vulkan
Reviewed-by: Bas Nieuwenhuizen
On Sun, Apr 23, 2017 at 9:22 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This just updates this to use the same flags as radeonsi
> for consistency.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_llvm_util.c | 2 +-
>
The Vulkan spec has
" Positive and negative infinities and positive and negative zeros are
generated as dictated by IEEE
754, but subject to the precisions allowed in the following table."
Sounds like we may need signed zero?
On Sun, Apr 23, 2017 at 9:15 PM, Dave Airlie wrote:
> From: Dave Airl
1-2 are
Reviewed-by: Bas Nieuwenhuizen
On Fri, Apr 21, 2017 at 4:41 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> In order to cleanly eliminate exports rewrite the
> code first to mirror how radeonsi works for now.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/comm
On Sun, Apr 23, 2017 at 8:54 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> Noticed while looking at Sascha Willems deferred shaders.
>
> This is a bit of an llvm workaround, llvm was producing this:
> v_cvt_pkrtz_f16_f32_e64 v4, v7, v8 ; D2960004
> 00021107
>
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 27 ---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 5 +
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h | 3 +++
3 files changed, 32 insertions(+), 3 deletions(-)
diff
v2: - Added some error handling.
- memset the buffer to 0.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 27 ---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 8 +++
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
v2: - Added some error handling.
- memset the buffer to 0.
v3: Added assert for buffer size.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 27 ---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c | 9
src/amd/vulkan
Reviewed-by: Bas Nieuwenhuizen
On Thu, Apr 27, 2017 at 1:35 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> Since the host pool changes,
>
> Fixes:
> dEQP-VK.api.descriptor_pool.out_of_pool_memory
>
> Fixes: 126d5ad "radv: Use host memory pool for non-freeable
Series is
Reviewed-by: Bas Nieuwenhuizen
On Wed, Apr 26, 2017 at 1:12 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This is ported from radeonsi, and I can see at least one
> Talos shader drops an export due to this, and saves some
> VGPR usage.
>
> v2: use shared co
Patch 1-3 are
Reviewed-by: Bas Nieuwenhuizen
On Thu, Apr 27, 2017 at 6:31 PM, Jason Ekstrand wrote:
> Reviewed-by: Iago Toral Quiroga
> ---
> src/compiler/spirv/nir_spirv.h | 1 +
> src/compiler/spirv/spirv_to_nir.c | 4
> src/compiler/spirv/vtn_variables.c | 4
Reviewed-by: Bas Nieuwenhuizen
On Fri, Apr 28, 2017 at 9:14 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This just aligns the code with radeonsi.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/radv_image.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 dele
Not much effect on dota2/talos, but positive on deferred.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_pipeline.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d6989137a55..7340675915f 100644
Set the bit in the same stage as the timestamp, instead always at top of pipe.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_query.c | 33 -
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan
Does not fix brokenness with the ready bit.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/sid.h| 1 +
src/amd/vulkan/radv_query.c | 38 ++
2 files changed, 27 insertions(+), 12 deletions(-)
diff --git a/src/amd/common/sid.h b/src/amd/common
onst VkExtent3D *extent)
> +{
> + if (memcmp(extent, &image->extent, sizeof(*extent)))
> + return false;
> + return true;
Can we remove the if statement here and just do return memcmp(...) == 0; ?
Other than that bikeshed:
Reviewed-by:
Series is
Reviewed-by: Bas Nieuwenhuizen
Fee free to disregard my comment on patch 1, given that its
implementation is almost immediately overwritten.
On Tue, May 2, 2017 at 2:22 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> Signed-off-by: Dave Airlie
> ---
>
Some defensive programming can't hurt.
Reviewed-by: Bas Nieuwenhuizen
On Tue, May 2, 2017 at 7:17 PM, Grazvydas Ignotas wrote:
> drmGetDevices2 takes count and not size. Probably hasn't caused problems
> yet in practice and was missed as setups with more than 8 DRM device
Reviewed-by: Bas Nieuwenhuizen
On Tue, May 2, 2017 at 7:17 PM, Grazvydas Ignotas wrote:
> After successful drmGetDevices2() call, drmFreeDevices() needs to be
> called.
>
> Fixes: 743315f2 "radv: do not open random render node(s)"
> Signed-off-by: Grazvydas Ignotas
All of the dynamic states apply to rasterization & fragment processing,
so we don't need to set them if we don't rasterize.
We don't clear the dirty flags for them though, so we don't miss any
updates for the next pipeline with rasterization.
Signed-off-by: Bas Nieuwenhu
Having it in the winsys didn't work when multiple devices use
the same winsys, as we then have multiple contexts per queue,
and each context counts separately.
Signed-off-by: Bas Nieuwenhuizen
Fixes: 7b9963a28f4 "radv: Enable userspace fence checking."
---
src/amd/vulka
Setting both offset to 0x20 and flat shade results in passthrough
mode instead of the constant.
Signed-off-by: Bas Nieuwenhuizen
Fixes: f205e19e4f8 "radv/ac: eliminate unused vertex shader outputs. (v2)"
---
src/amd/vulkan/radv_pipeline.c | 8
1 file changed, 4 insert
Reviewed-by: Bas Nieuwenhuizen
On Thu, May 4, 2017 at 2:52 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> There is no reason to advertise transfer ability for formats we can't
> use for anything else. This stops some CTS tests hitting internal
> error for 64-bit typ
Can't we just use a non-SRGB image view into the destination image?
That should save some operations.
On Thu, May 4, 2017 at 5:27 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> If we are resolving into an srgb dest, we need to convert
> to linear so the store does the conversion back.
>
> This s
Reviewed-by: Bas Nieuwenhuizen
Maybe nominate for stable too?
On Fri, May 5, 2017 at 2:28 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This just adds the chip in the right places.
>
> We don't set the partial_vs_wave workaround, as radeonsi
> doesn't, but have
Reviewed-by: Bas Nieuwenhuizen
On Tue, May 2, 2017 at 10:05 PM, Grazvydas Ignotas wrote:
> valgrind reports them as leaked, and I could not find anything making a
> copy of the nir pointer. Also, radv_device_init_meta_blit_color() is
> already freeing them unconditionally like this.
&
Reviewed-by: Bas Nieuwenhuizen
On Sun, May 7, 2017 at 11:54 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> As I pointed out for radeonsi, and AMD confirmed, so fix this
> in radv as well.
>
> Cc: "17.1"
> Signed-off-by: Dave Airlie
> ---
> src/amd/vul
This series is
Reviewed-by: Bas Nieuwenhuizen
On Thu, May 4, 2017 at 5:27 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> If we are resolving into an srgb dest, we need to convert
> to linear so the store does the conversion back.
>
> This should fix some wierdness seen w
This series is
Reviewed-by: Bas Nieuwenhuizen
On Fri, May 5, 2017 at 2:59 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This isn't necessary yet but I'd like to use the range in
> some future patches.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/
We processed fs key 3 multiple times, resulting in overwriting the
pointer in the meta struct and hence only freeing one of them.
Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_resolve_fs.c
Totally independent.
Signed-off-by: Bas Nieuwenhuizen
Fixes: 0e6d532d327 "radv/meta: add support for save/restore meta without vertex
data."
---
src/amd/vulkan/radv_meta.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_meta.c b/src/
Nack. We had that and Andres removed it due to high priority interactions.
On 9 Nov 2017 18:01, "Samuel Pitoiset" wrote:
Copied from RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/si_cmd_buffer.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --gi
rek
>
> On Thu, Nov 9, 2017 at 6:22 PM, Bas Nieuwenhuizen
> wrote:
>> Nack. We had that and Andres removed it due to high priority interactions.
>>
>>
>> On 9 Nov 2017 18:01, "Samuel Pitoiset" wrote:
>>
>> Copied from RadeonSI.
>>
>&g
Reviewed-by: Bas Nieuwenhuizen
On 10 Nov 2017 00:45, "Chad Versace" wrote:
> Use the host arch, not the target arch. In Meson and in recent
> Autotools, the host arch is where the binary will be used. The target
> arch is useful only when compiling a compiler.
>
> S
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Wed, Nov 8, 2017 at 12:12 PM, Samuel Pitoiset
wrote:
> Just after the vertex shader.
>
> This seems to give a minor boost for, at least, Serious Sam
> Fusion 2017 and Dawn of War 3. I don't see any real impacts
> with
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Wed, Nov 8, 2017 at 12:52 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 2 +-
> src/amd/vulkan/radv_private.h| 3 +--
> 2 files changed, 2 insertions(+), 3 deleti
For the series:
Reviewed-by: Bas Nieuwenhuizen
On Fri, Nov 10, 2017 at 9:18 AM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd
Reviewed-by: Bas Nieuwenhuizen
for the series, if you hadn't forgotten/pushed this yet. Sorry for the delay.
On Mon, Nov 6, 2017 at 3:05 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This register is the same on all gpus so far, so emit it in one
> place and also for the
Reviewed-by: Bas Nieuwenhuizen
Maybe time to index shaders based on HW stage instead of API stage?
On Mon, Nov 6, 2017 at 5:57 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This should reduce some pointless loops.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/vulkan/r
Otherwise we leak it.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
---
src/amd/vulkan/radv_device.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 4e3ad111382..6
Otherwise we can leak the old syncobj.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
---
src/amd/vulkan/radv_device.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 929082182c
Reviewed-by: Bas Nieuwenhuizen
On Tue, Nov 14, 2017 at 4:38 PM, Samuel Pitoiset
wrote:
> radv_fill_buffer() ensures that the image BO is added to the list.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 2 --
> 1 file changed, 2 deletions(-)
&g
Reviewed-by: Bas Nieuwenhuizen
On Tue, Nov 14, 2017 at 5:29 PM, Samuel Pitoiset
wrote:
> VkDeviceQueueCreateInfo::queueFamilyIndex is an unsigned 32-bit
> integer.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_device.c | 2 +-
> src/amd/vulkan/radv_
Reviewed-by: Bas Nieuwenhuizen
On Tue, Nov 14, 2017 at 4:38 PM, Samuel Pitoiset
wrote:
> radv_fill_buffer() ensures that the image BO is added to the list.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 2 --
> 1 file changed, 2 deletions(-)
&g
For the series
Reviewed-by: Bas Nieuwenhuizen
On Tue, Nov 14, 2017 at 5:27 PM, Samuel Pitoiset
wrote:
> I don't think we will need a 64-bit unsigned integer for the
> dirty flags in the future, and there is still 20 bits left.
>
> Signed-off-by: Samuel Pitoiset
> -
I suspect this doesn't do what you'd expect. IIRC specifying online in a
function in a .c file is pretty much useless because it only changes
linking mode, not actually online's it.
On 15 Nov 2017 15:43, "Samuel Pitoiset" wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_
The series is
Reviewed-by: Bas Nieuwenhuizen
On Wed, Nov 15, 2017 at 3:43 PM, Samuel Pitoiset
wrote:
> aspects can't be zero and there is an assertion that ensures
> it's not in emit_clear().
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffe
Reviewed-by: Bas Nieuwenhuizen
On Wed, Nov 15, 2017 at 10:55 AM, Samuel Pitoiset
wrote:
> As per the spec, the query identified by queryPool and query
> must currently be active. Applications have to call vkCmdBeginQuery()
> before, and thus the query pool BO will already be in
You'll want to change the title to 16 words instead of 16 bytes. Otherwise
Reviewed-by: Bas Nieuwenhuizen
On Wed, Nov 15, 2017 at 12:08 PM, Samuel Pitoiset
wrote:
> This allows to update them with only one memcpy().
>
> Signed-off-by: Samuel Pitoiset
> ---
Reviewed-by: Bas Nieuwenhuizen
On Thu, Nov 30, 2017 at 8:58 PM, Samuel Pitoiset
wrote:
> The state no longer exists on GFX9.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_device.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> dif
Reviewed-by: Bas Nieuwenhuizen
On Thu, Nov 30, 2017 at 2:32 PM, Samuel Pitoiset
wrote:
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 7 ---
> src/amd/vulkan/radv_device.c | 3 ---
> src/amd/vulkan/radv_private.h| 1 -
> 3 files cha
Reviewed-by: Bas Nieuwenhuizen
On Thu, Nov 30, 2017 at 10:16 PM, Samuel Pitoiset
wrote:
> It's really annoying and this pollutes the output especially
> when a bunch of non-meta shaders are compiled.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_pipel
Reviewed-by: Bas Nieuwenhuizen
On Thu, Nov 30, 2017 at 10:23 PM, Samuel Pitoiset
wrote:
>"vkAllocateCommandBuffers can be used to create multiple command
> buffers. If the creation of any of those command buffers fails, the
> implementation must destroy all succes
There is no chain, so checking the length ends with a SEGFAULT.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103579
Cc:
---
src/compiler/spirv/vtn_variables.c | 58 --
1 file changed, 30 insertions(+), 28 deletions(-)
diff --git a/src/compiler/spir
Reviewed-by: Bas Nieuwenhuizen
On Mon, Dec 4, 2017 at 3:32 PM, Samuel Pitoiset
wrote:
> module can be NULL, oops.
>
> v2: really check that module is not NULL
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_shader.h | 4 ++--
> 1 file changed, 2 in
The series is
Reviewed-by: Bas Nieuwenhuizen
Tested-by: Bas Nieuwenhuizen
On Fri, Jun 16, 2017 at 10:09 PM, Emil Velikov wrote:
> From: Emil Velikov
>
> The commit did not add the relevant includes - in particular
> stdint.h and stdbool.h for the respective standard types.
>
Signed-off-by: Bas Nieuwenhuizen
Fixes: 0628580eff6 "radv: Specify semantics of HTILE layout helpers."
---
src/amd/vulkan/radv_meta_blit2d.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_blit2d.c
b/src/
On Tue, Jun 20, 2017 at 6:38 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> Noticed in passing.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/common/ac_nir_to_llvm.c | 5 +++--
> src/amd/common/ac_nir_to_llvm.h | 1 +
> src/amd/vulkan/si_cmd_buffer.c | 6 ++
> 3 files changed, 10 insertio
Reviewed-by: Bas Nieuwenhuizen
for the series.
On Tue, Jun 20, 2017 at 6:38 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> Fixes:
> dEQP-VK.pipeline.framebuffer_attachment.no_attachments
> dEQP-VK.pipeline.framebuffer_attachment.no_attachments_ms
>
> Signed-off-by: Dave
On Sun, Jun 25, 2017 at 9:42 PM, Dave Airlie wrote:
> On 25 June 2017 at 04:58, Bas Nieuwenhuizen wrote:
>> Signed-off-by: Bas Nieuwenhuizen
>> Fixes: 0628580eff6 "radv: Specify semantics of HTILE layout helpers."
>> ---
>> s
v2: Don't pass layout to image view usage mask.
Signed-off-by: Bas Nieuwenhuizen
Fixes: 0628580eff6 "radv: Specify semantics of HTILE layout helpers."
---
src/amd/vulkan/radv_meta_blit2d.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a
On Sun, Jun 25, 2017 at 10:29 PM, Dave Airlie wrote:
> On 26 June 2017 at 06:19, Bas Nieuwenhuizen wrote:
>> v2: Don't pass layout to image view usage mask.
>>
>> Signed-off-by: Bas Nieuwenhuizen
>> Fixes: 0628580eff6 "radv: Specify semantics of HTILE lay
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_image.c | 6 ++
src/amd/vulkan/radv_meta_blit.c | 12 ++--
src/amd/vulkan/radv_meta_blit2d.c | 16 +++-
src/amd/vulkan/radv_meta_bufimage.c | 13 ++---
src/amd/vulkan/radv_meta_clear.c
Thanks, pushed patches 2& 3.
On Mon, Jun 26, 2017 at 10:05 AM, Nicolai Hähnle wrote:
> Patches 2 & 3:
>
> Reviewed-by: Nicolai Hähnle
>
>
> On 23.06.2017 12:18, James Legg wrote:
>>
>> ---
>> src/amd/common/ac_nir_to_llvm.c | 17 -
>> 1 file changed, 12 insertions(+), 5 deleti
Thanks, pushed.
On Mon, Jun 26, 2017 at 6:17 PM, Alex Smith wrote:
> The buffer intrinsics should be used instead of the image ones.
>
> Signed-off-by: Alex Smith
> Cc:
> ---
> This applies on top of James Legg's recent series [1], since they both
> touch the same function.
>
> [1] https://list
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_blit.c | 4 ++--
src/amd/vulkan/radv_meta_blit2d.c | 4 ++--
src/amd/vulkan/radv_meta_clear.c | 2 +-
src/amd/vulkan/radv_meta_decompress.c | 2 +-
src/amd/vulkan/radv_pipeline.c| 22
We have some cases where changing between depth and stencil only aspect
was causing hangs.
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index
We apparently still used v16i8
As radeonsi doesn't use it with LLVM version checks I don't think
we need them either.
Signed-off-by: Bas Nieuwenhuizen
CC: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/
You may need to remove
if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
goto fail;
On Mon, Jun 26, 2017 at 3:49 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> We can only fast clear 128-bit images if the r/g/b channels
> are the same, and we are using DCC.
>
> For DCC we
Reviewed-by: Bas Nieuwenhuizen
On Mon, Jun 26, 2017 at 3:49 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> This doesn't get used yet, it just adds support to various PKT3
> emissions to enable it later.
>
> Signed-off-by: Dave Airlie
> ---
> src/amd/
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