_ud(0x0f00));
> - brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
> - brw_OR(p, addr, addr, temp);
> + /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
> + brw_MUL(p, addr, sampler_reg, brw_imm_ud(0x101));
> + brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
> + brw_AND(p,
return brw->gen >= 9 ? 16 : 4;
> + return brw->gen >= 9 ? j * 4 : 4;
> + }
>
> if (format == MESA_FORMAT_S_UINT8)
>return brw->gen >= 7 ? 8 : 4;
> --
> 2.4.1
>
> ___
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>
On Fri, Apr 24, 2015 at 10:54 AM, Anuj Phogat wrote:
> On Thu, Apr 23, 2015 at 4:38 PM, Pohjolainen, Topi
> wrote:
>> On Fri, Apr 17, 2015 at 04:51:23PM -0700, Anuj Phogat wrote:
>>> This refactoring is required by later patches in this series.
>>>
sed,
> - fetch_compressed,
> - fetch_compressed
> - },
> + FETCH_COMPRESSED(ETC1_RGB8),
> + FETCH_COMPRESSED(ETC2_RGB8),
> + FETCH_COMPRESSED(ETC2_SRGB8),
> + FETCH_COMPRESSED(ETC2_RGBA8_EAC),
> + FETCH_COMPRESSED(ETC2_SRGB8_ALPHA8_EAC),
> + FETCH_CO
RGBA;
> + default:
> + ; /* fallthrough */
> + }
> + }
> +
> if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility) {
>switch (internalFormat) {
>case GL_COMPRESSED_RGB8_ETC2:
> --
> 2.4.1
>
> __
and change the name to brw_miptree_choose_tiling().
V3: Remove redundant function parameters. (Topi)
Signed-off-by: Anuj Phogat
Reviewed-by: Topi Pohjolainen
---
Comment made by Topi on patch 02/22 is fixed in V3 of this patch.
src/mesa/drivers/dri/i965/brw_tex_layout.c| 107
BRW_SFID_SAMPLER, dst, src, addr);
> --
> 1.9.3
>
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Fixes 3 failing sampler_array_indexing tests on skl:
gs-nonzero-base, gs-sim
R:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_10x10_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x10_KHR:
> + case GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
> return GL_TRUE;
> default:
>return GL_FALSE;
> --
> 2.4.1
>
> _
se GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR:
> + return ctx->Extensions.KHR_texture_compression_astc_ldr;
> case GL_PALETTE4_RGB8_OES:
> case GL_PALETTE4_RGBA8_OES:
> case GL_PALETTE4_R5_G6_B5_OES:
> --
> 2.4.1
>
> _____
GLboolean KHR_texture_compression_astc_ldr;
> GLboolean MESA_pack_invert;
> GLboolean MESA_ycbcr_texture;
> GLboolean NV_conditional_render;
> --
> 2.4.1
>
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B8_ALPHA8:
> + return GL_COMPRESSED_SRGB8_ALPHA8_ASTC_12x12_KHR;
> +
> default:
>_mesa_problem(ctx, "Unexpected mesa texture format in"
> " _mesa_compressed_format_to_glenum()");
> --
> 2.4.1
>
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RMAT_B8G8R8X8_SRGB:
> - case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM:
> - return GL_SRGB;
> - default:
> - return GL_LINEAR;
> - }
> + const struct gl_format_info *info = _mesa_get_format_info(format);
> + return info->IsSRGBFormat ? GL_SRGB : GL_LINEAR;
&g
Patch sets the alignments for texture and renderbuffer surfaces.
V3: Make changes inside horizontal_alignment() and
vertical_alignment() (Topi)
Signed-off-by: Anuj Phogat
Cc: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 32 +-
1 file
Signed-off-by: Anuj Phogat
Cc: Ben Widawsky
---
Patch can be squashed with 17/22. I kept it separate for easy review.
src/mesa/drivers/dri/i965/intel_blit.c | 93 ++
1 file changed, 61 insertions(+), 32 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
()
Move overlap computation inside intel_miptree_blit().
Use XY_FAST prefix for the macros.
Signed-off-by: Anuj Phogat
Cc: Ben Widawsky
---
src/mesa/drivers/dri/i965/intel_blit.c | 306 +++
src/mesa/drivers/dri/i965/intel_blit.h | 2 +
src/mesa/drivers
brw_miptree_choose_tr_mode() actually choose TRMODE. (Ben)
Few cosmetic changes.
Signed-off-by: Anuj Phogat
Cc: Ben Widawsky
---
I think we need some benchmarking to come up with conditions to
choose Ys (64 KB) over Yf (4 KB). Any thoughts on minimum texture
size so that 64 KB tiling is
On Wed, Jun 3, 2015 at 3:25 PM, Ben Widawsky wrote:
> On Tue, Jun 02, 2015 at 04:04:07PM -0700, Anuj Phogat wrote:
>> This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
>> It can be later turned on for other tiling patterns (X,Y) too.
>>
>> V3:
FETCH_NULL(ASTC_8x5_RGBA),
> + FETCH_NULL(ASTC_8x6_RGBA),
> + FETCH_NULL(ASTC_8x8_RGBA),
> + FETCH_NULL(ASTC_10x5_RGBA),
> + FETCH_NULL(ASTC_10x6_RGBA),
> + FETCH_NULL(ASTC_10x8_RGBA),
> + FETCH_NULL(ASTC_10x10_RGBA),
> + FETCH_NULL(ASTC_12x10_RGBA),
> + FETCH_NULL(ASTC_12x12_RGBA),
> + FETCH_NULL(ASTC_4x4_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_5x4_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_5x5_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_6x5_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_6x6_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_8x5_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_8x6_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_8x8_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_10x5_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_10x6_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_10x8_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_10x10_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_12x10_SRGB8_ALPHA8),
> + FETCH_NULL(ASTC_12x12_SRGB8_ALPHA8)
> };
>
>
> --
> 2.4.1
>
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quot;/>
>
> -
> + xmlns:xi="http://www.w3.org/2001/XInclude"/>
>
> http://www.w3.org/2001/XInclude"/>
>
> --
> 2.4.1
>
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On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote:
> From: Nanley Chery
>
> - Remove redundant checks and comments by grouping our calculations for
> align_w and align_h wherever possible.
> - Don't pass more parameters than necessary.
> - Minor code simplifications.
>
> Signed-off-by: Nanley
ut,
> * whomever forgot to undo the multiply by 4.
> */
> - if (brw->gen >= 8 || brw->is_haswell)
> + if (brw->gen == 8 || brw->is_haswell)
> query->Base.Result /= 4;
>break;
>
> --
> 2.4.2
>
LGTM. Tested on Skylake.
for gens in above function (Chad)
bonus 'for'
>
> Signed-off-by: Ben Widawsky
> Cc: Chad Versace
> Cc: Topi Pohjolainen
> Reviewed-by: Jordan Justen
> Reviewed-by: Anuj Phogat
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36
> +++-
On Tue, Jun 2, 2015 at 2:51 PM, Anuj Phogat wrote:
> Patch sets the alignments for texture and renderbuffer surfaces.
>
> V3: Make changes inside horizontal_alignment() and
> vertical_alignment() (Topi)
>
> Signed-off-by: Anuj Phogat
> Cc: Topi Pohjolainen
> ---
>
Avoids a crash in case of negative array index is used in a
shader program.
Cc:
Signed-off-by: Anuj Phogat
---
src/glsl/ast_array_index.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index 5ca85f6
Currently Mesa crashes with a shader like this:
[fragmnet shader]
float[5] array;
int idx = -2;
void main()
{
gl_FragColor = vec4(0.0, 1.0, 0.0, array[idx]);
}
Cc:
Signed-off-by: Anuj Phogat
---
src/glsl/opt_array_splitting.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Emit a warning to let user know that the behavior is undefined.
Cc:
Signed-off-by: Anuj Phogat
---
src/glsl/ast_array_index.cpp | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index 299ec91..b23bb69
Currently abort happens for this shader:
[fragment shader]
float array[5];
const int idx = 8;
void main()
{
gl_FragColor = vec4(0.0, 1.0, 0.0, array[idx]);
}
Cc:
Signed-off-by: Anuj Phogat
---
src/glsl/ir_validate.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/glsl
Variables are used in later patches to implement
EXT_framebuffer_multisample_blit_scaled extension.
Signed-off-by: Anuj Phogat
---
src/mesa/main/mtypes.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 0d50be8..1cb3461 100644
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_context.c | 36 +
1 file changed, 36 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 619f2d5..cabc79f 100644
--- a/src/mesa/drivers
ple msaa resolve shader for scaled resolves with scaling
factor = 1.0.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/common/meta.h | 6 ++
src/mesa/drivers/common/meta_blit.c | 198 +---
2 files changed, 191 insertions(+), 13 deletions(-)
diff --git a/
{
> + return !strncmp(name, "#anon", 5);
> + }
> +
> + /**
> * Get the type stripped of any arrays
> *
> * \return
> --
> 1.9.3
>
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On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg wrote:
> From: Damien Lespiau
>
> This commands has seen the addition of 2 dwords that allow to specify
> which channels of which attributes need to be forwarded to the fragment
> shader.
>
> v2: Rebase forward a year (done by Ken).
>
> Signed-o
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Patches 1-8 are Reviewed-by: Anuj Phogat
Will review rest of the patches tomorrow.
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On Wed, Sep 24, 2014 at 5:54 PM, Anuj Phogat wrote:
> On Wed, Sep 24, 2014 at 12:28 PM, Kristian Høgsberg
> wrote:
>> Here's a set of 16 patches to bring up mesa on Skylake (GEN 9). This is
>> just initial enabling, there's more work to do. Most patches have bee
On Fri, Sep 26, 2014 at 12:50 PM, Jordan Justen wrote:
> On Tue, Sep 23, 2014 at 5:38 PM, Anuj Phogat
> wrote:
> > Variables are used in later patches to implement
> > EXT_framebuffer_multisample_blit_scaled extension.
> >
> > Signed-off-by: Anuj Phogat
> >
with values specific to Intel hardware.
V2: Define and use gen6_get_sample_map() function to initialize
the variables.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_context.c| 8
src/mesa/drivers/dri/i965/brw_context.h| 2 +
src/mesa/drivers
SampleMap{2,4,8}x variables are used in later patches to implement
EXT_framebuffer_multisample_blit_scaled extension.
V2: Use integer array instead of a string.
Bump up the comment.
Signed-off-by: Anuj Phogat
---
src/mesa/main/mtypes.h | 32
1 file changed
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_extensions.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 046d2a1..10fe10e 100644
--- a/src/mesa/drivers/dri
ple msaa resolve shader for scaled resolves with scaling
factor = 1.0.
V3:
- Make changes to create a string out of ctx->Const.SampleMap{2,4,8}x
variables and use it in fragment shader.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/common/meta.h | 6 ++
src/mesa/dri
On Mon, Sep 29, 2014 at 7:16 PM, Jordan Justen wrote:
>
> On 2014-09-29 16:33:33, Anuj Phogat wrote:
> > SampleMap{2,4,8}x variables are used in later patches to implement
> > EXT_framebuffer_multisample_blit_scaled extension.
> >
> > V2: Use integer array instead of
SampleMap{2,4,8}x variables are used in later patches to implement
EXT_framebuffer_multisample_blit_scaled extension.
V2: Use integer array instead of a string.
Bump up the comment.
V3: Use uint8_t type array.
Signed-off-by: Anuj Phogat
---
src/mesa/main/mtypes.h | 32
with values specific to Intel hardware.
V2: Define and use gen6_get_sample_map() function to initialize
the variables.
V3: Change the function name to gen6_set_sample_maps() and use
memcpy() to fill in the data.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_context.c
ple msaa resolve shader for scaled resolves with scaling
factor = 1.0.
V3:
- Make changes to create a string out of ctx->Const.SampleMap{2,4,8}x
variables and use it in fragment shader.
V4:
- Make changes to use uint8_t type ctx->Const.SampleMap{2,4,8}x
variables.
Signed-off-b
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_extensions.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 046d2a1..10fe10e 100644
--- a/src/mesa/drivers/dri
T(opt_copy_propagation);
> - OPT(opt_algebraic);
>OPT(opt_cse);
> + OPT(opt_algebraic);
>OPT(opt_register_coalesce);
> } while (progress);
>
> --
> 1.8.5.5
>
> ______
l;
> bool success = data[offset] == expected_value;
> drm_intel_bo_unmap(brw->batch.workaround_bo);
>
> --
> 2.1.2
>
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Nice catch.
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Leaving the issue of how other drivers can make use of this new state flag,
this series is Reviewed-by: Anuj Phogat
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Velikov
> wrote:
>> Hi Anuj,
>>
>> Afaics the series is yet to land on master, this I've not pulled it for
>> the stable branch. Is the lack of review holding it back ?
>>
>> Gents can anyone take a look at/review the series ?
>>
>> Thanks
>
(1 << num_samples) - 1 : 1);
> gen6_blorp_emit_state_base_address(brw, params);
> gen6_blorp_emit_vertices(brw, params);
> gen7_blorp_emit_urb_config(brw, params);
> --
> 2.1.2
>
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Looks good to me. Verified the requirement in IVB PRM.
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}
> - assert(this->result.is_valid_3src());
> + assert(this->result.file == GRF || this->result.file == UNIFORM);
>op[operand] = this->result;
>
>/* Matrix expression operands should have been broken down to vector
> --
> 2.0.4
>
&g
LSL_TYPE_FLOAT, components, vectors, count,
> bool(transpose), shProg, location, uni);
> }
> --
> 1.8.1.4
>
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Series is Reviewed-by: Anuj
This patch fixes the misrendering in etqw-demo.
https://bugs.freedesktop.org/show_bug.cgi?id=89039
Tested-by: Anuj Phogat
On Fri, Mar 13, 2015 at 9:29 AM, Neil Roberts wrote:
> Commit 0ac4c272755c7 made it add a header for the send message when
> using SIMD4x2 on Skylake because withou
On Wed, Mar 18, 2015 at 1:06 PM, Laura Ekstrand wrote:
> So it turns out that this doesn't actually fix any bugs or add any features,
> stictly speaking. However, it does avoid a lot of kludginess. Previously, if
> you called
>
> glCopyTextureSubImage3D(texcube, 0, 0, 0, zoffset = 3, ...
>
> it w
ure, GLint
> level,
> GL_TEXTURE_CUBE_MAP_POSITIVE_X + zoffset,
> level,
> xoffset, yoffset, 0,
> - x, y, width, height, false);
> + x, y, width, height, self);
> }
> else
>_mesa_copy_texture_sub_image(ctx, 3, texObj, texObj->Target, level,
> xoffset, yoffset, zoffset,
> - x, y, width, height, true);
> + x, y, width, height, self);
> }
>
> static bool
> diff --git a/src/mesa/main/teximage.h b/src/mesa/main/teximage.h
> index 0ce4a30..1eebaa8 100644
> --- a/src/mesa/main/teximage.h
> +++ b/src/mesa/main/teximage.h
> @@ -196,7 +196,8 @@ _mesa_copy_texture_sub_image(struct gl_context *ctx,
> GLuint dims,
> GLenum target, GLint level,
> GLint xoffset, GLint yoffset, GLint zoffset,
> GLint x, GLint y,
> - GLsizei width, GLsizei height, bool dsa);
> + GLsizei width, GLsizei height,
> + const char *caller);
>
> extern void
> _mesa_texture_image_multisample(struct gl_context *ctx, GLuint dims,
> --
> 2.1.0
>
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On Thu, Mar 19, 2015 at 10:56 AM, Laura Ekstrand wrote:
>
>
> On Wed, Mar 18, 2015 at 3:15 PM, Anuj Phogat wrote:
>>
>> On Wed, Mar 18, 2015 at 1:06 PM, Laura Ekstrand
>> wrote:
>> > So it turns out that this doesn't actually fix any bugs or add any
>
On Fri, Mar 6, 2015 at 4:15 PM, Anuj Phogat wrote:
> in different fragment shaders. This also applies to a case when gl_FragCoord
> is redeclared with no layout qualifiers in one fragment shader and not
> declared but used in other fragment shader.
>
> Signed-off-by: Anuj Phogat
object)",
>> + caller, buffer);
>> + return NULL;
>> + }
>>
>> return bufObj;
>> }
>> --
>> 2.1.4
>>
>
>
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red closer together physically;
> -* the real distance is (qpitch / block height).
> +* The value is the one that is sent in the surface state. The actual
> +* meaning depends on certain criteria. Usually it is simply the number of
> +* uncompressed rows between each slice. However on Gen9+ for compressed
> +* su
On Fri, Feb 20, 2015 at 2:31 PM, Neil Roberts wrote:
> On Gen9+ the 1D miptree is laid out with all of the mipmap levels in a
> horizontal line.
> ---
> src/mesa/drivers/dri/i965/brw_tex_layout.c | 62
> +-
> 1 file changed, 60 insertions(+), 2 deletions(-)
>
> diff -
gt; References: https://bugs.freedesktop.org/show_bug.cgi?id=89039 (doesn't fix)
> Cc: Anuj Phogat
> Cc: Eero Tamminen
> Signed-off-by: Ben Widawsky
> ---
> src/mesa/drivers/dri/i965/gen8_depth_state.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff -
view comments while I work
on fixing the piglit regressions.
Note: My drm patches posted on intel-gfx are required to build
this series.
Patches are available at:
https://github.com/aphogat/drm.git, branch: tiling-yf-ys
https://github.com/aphogat/mesa.git, branch: tiling-yf-ys
Anuj Phogat (18):
From: Anuj phogat
This refactoring is required by later patches in this series.
Signed-off-by: Anuj phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 13 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 ++-
src/mesa/drivers/dri/i965
This function will be utilised in later patches.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_context.h| 4
src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index c4fd3a2..b3d7c1b 100644
--- a/src/mesa
This will allow Skylake to use _mesa_meta_pbo_GetTexSubImage() for reading YF/YS
tiled surfaces.
V2: Make changes suggested by Neil.
Signed-off-by: Anuj Phogat
Cc: Neil Roberts
---
src/mesa/drivers/common/meta.h | 1 +
src/mesa/drivers/common/meta_tex_subimage.c | 45
From: Anuj phogat
Patch continues code refactoring.
Signed-off-by: Anuj phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 105 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8
From: Anuj phogat
and some more code refactoring. No functional changes in this patch.
Signed-off-by: Anuj phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 89 --
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Note: Buffer size condition used in this patch to choose between
YF / YS tiling is just a place holder. I need some suggestions
here.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 79 ++
1 file changed, 79 insertions(+)
diff --git a/src
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 03db100..8e845c6 100644
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1c9f2fe..499c2dc 100644
--- a/src/mesa
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 7 ---
src/mesa/drivers/dri/i965/intel_tex_image.c | 15 ---
2 files changed, 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
Currently, that's the only path that supports reading data from these buffers.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read
From: Anuj phogat
Patch sets the alignments for texture and renderbuffer surfaces.
Signed-off-by: Anuj phogat
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 28 ++
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 7f82f53..97f9422 100644
--- a/src/mesa/drivers/dri/i965
vel 0 shows up right but miplevels > 0 are
incorrect. So, I'm not sure if this patch is the right thing to do.
It just helps move things forward at the moment.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_defines.h| 3 +++
src/mesa/drivers/dri/i965/gen8_surface
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 39fb3b1..c4fd3a2 100644
--- a/src/mesa/drivers/dri/i965
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_blit.c | 293 +++
src/mesa/drivers/dri/i965/intel_blit.h | 3 +
src/mesa/drivers/dri/i965/intel_copy_image.c | 3 +
src/mesa/drivers/dri/i965/intel_reg.h| 33 +++
4 files changed, 292
Conditions modified allow skl+ to use blitter:
- for all tiling formats
- to write data to YF/YS tiled surfaces
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 80 ++
1 file changed, 80 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index eab3884..39fb3b1 100644
--- a/src/mesa
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 499c2dc
No other path currently supports uploading data to these surfaces.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa
From: Anuj phogat
This patch sets the tiled resource mode for texture and renderbuffer
surfaces.
Signed-off-by: Anuj phogat
---
src/mesa/drivers/dri/i965/brw_defines.h| 8
src/mesa/drivers/dri/i965/gen8_surface_state.c | 22 ++
2 files changed, 30
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index fac7b8e..ef6ff11 100644
--- a/src/mesa
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965
On Mon, Mar 30, 2015 at 2:42 PM, Matt Turner wrote:
> On Mon, Mar 30, 2015 at 2:04 PM, Anuj Phogat wrote:
>> This series enables skl+ to read/write data to YF/YF tiled
>> surfaces. Many piglit tests for texture/buffer data read/write
>> pass with the new tiling formats. I&
No other path currently supports uploading data to these surfaces.
Fixes the incorrect rendering in miplevels > 0 with YF/YS tiling.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 23 +--
1 file changed, 21 insertions(+), 2 deleti
V2: Make relevant changes in intelTexSubImage().
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 7 ---
src/mesa/drivers/dri/i965/intel_tex_image.c| 15 ---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 7 ---
3 files changed, 29
if (base_format != GL_DEPTH_COMPONENT &&
> - base_format != GL_DEPTH_STENCIL)
> + base_format != GL_DEPTH_STENCIL &&
> + base_format != GL_STENCIL_INDEX)
> return true;
> }
>
> --
> 1.9.3
>
Reviewed-by: Anuj Phogat
On Tue, Mar 31, 2015 at 12:13 PM, Chris Forbes wrote:
> I'd adjust the write to surf[0] to use surf_type too.
I'll fix that. Thanks.
>
> Other than that, this patch is:
>
> Reviewed-by: Chris Forbes
>
> On Tue, Mar 31, 2015 at 10:04 AM, Anuj Phogat wrote:
>&g
d required_glsl_version,
> --
> 1.9.1
>
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Reviewed-by: Anuj Phogat
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int i = brw->gen >= 9 ? 2 : 1; i < coord_components; i++) {
> emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
> coordinate = offset(coordinate, 1);
> length++;
> --
> 1.9.3
>
> _
> _______
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LGTM
Reviewed-by: Anuj Phogat
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mpile_error(ctx, err, __func__);
>
>
> /* Only one size for each attribute may be active at once. Eg. if
> --
> 1.7.9.5
>
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Both patches are:
Reviewed-by: Anuj Phogat
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types(inst));
> + for (int i = 0; i < inst->sources; i++)
> +inst->src[i].type = entry->dst.type;
> + inst->dst.type = entry->dst.type;
> + }
> +
> + if (!inst->src[arg].abs) {
> + inst->src[arg].abs = entry->src.abs;
> +
SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
> SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) |
> --
> 2.1.4
>
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s in this family
> * cannot render to XRGB targets. This means that we have to
> --
> 2.3.5
>
> Reviewed-by: Anuj Phogat
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_read_offset,
> SO_STREAM_2_VERTEX_READ_OFFSET);
> + dw2 |= SET_FIELD(urb_entry_read_length - 1,
> SO_STREAM_2_VERTEX_READ_LENGTH);
>
> - dw2 |= urb_entry_read_offset <<
> SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT;
> - dw2 |= (urb_entry_read_length - 1) <<
> SO_STREAM_3_VERTEX_READ_L
1_negate) != (ys0_negate != ys1_negate);
>return ret;
> } else if (!a->is_commutative()) {
>bool match = true;
> --
> 2.0.5
>
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This enables using _mesa_meta_pbo_TexSubImage() to upload data
to R16G16B16X16 texture. Earlier it fell back to slower paths.
Jenkins run shows no piglit regressions.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_surface_formats.c | 6 ++
1 file changed, 6 insertions
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