Re: [Mesa-dev] [PATCH 23/25] radeonsi: factor si_query_buffer logic out of si_query_hw

Thanks! On 06.02.19 01:27, Timothy Arceri wrote: > On 4/2/19 11:26 pm, Nicolai Hähnle wrote: >> On 01.02.19 05:25, Timothy Arceri wrote: >>> On 26/1/19 11:56 am, Marek Olšák wrote: Timothy, can you please test the attached fix? >>> >>> I'm having trouble compiling 32bit mesa on my machine at

[Mesa-dev] [PATCH v3 00/44] VK_KHR_shader_float_controls implementation for ANV

Hello, This is the third version of the VK_KHR_shader_float_controls implementation for Intel's Vulkan driver, ANV. You can clone this branch by executing this command: $ git clone -b siglesias/VK_KHR_shader_float_controls-v3 \ https://github.com/Igalia/mesa.git Remember that this branch depend

[Mesa-dev] [PATCH v3 01/44] spirv: check support for SPV_KHR_shader_float_controls capabilities

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index e9d887a8f4b..45fb00a9cfe 100644 --- a/src/compiler/shad

[Mesa-dev] [PATCH v3 03/44] nir: add auxiliary functions to detect if a mode is enabled

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 66 ++ 1 file changed, 66 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 740c64d2a94..a84c46507e2 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler

[Mesa-dev] [PATCH v3 05/44] spirv/glsl450: fix atan2(0, 0) lowering

We were returning 3*pi/4 when we should return 0.0 according to IEEE 754. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c

[Mesa-dev] [PATCH v3 02/44] spirv/nir: keep track of SPV_KHR_shader_float_controls execution modes

v2: - Add support for rounding modes for each floating point bit size. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/shader_enums.h | 20 +++ src/compiler/shader_info.h| 3 +++ src/compiler/spirv/spirv_to_nir.c | 41 +++ 3 files

[Mesa-dev] [PATCH v3 04/44] nir: add support for flushing to zero denorm constants

v2: - Refactor conditions and shared function (Connor) - Move code to nir_eval_const_opcode() (Connor) - Don't flush to zero on fquantize2f16 From Vulkan spec, VK_KHR_shader_float_controls section: "3) Do denorm and rounding mode controls apply to OpSpecConstantOp? RESOLVED: Yes, except whe

[Mesa-dev] [PATCH v3 14/44] nir: add new fdot* opcodes taking into account rounding mode

According to Vulkan spec, the new execution modes affect only correctly rounded SPIR-V instructions, which includes FaceForward. FaceForward is lowered into fdot* instructions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_builder.h | 32 +++ src/comp

[Mesa-dev] [PATCH v3 10/44] nir: add rounding mode support to Opcode class in nir_opcodes.py

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h| 3 ++ src/compiler/nir/nir_opcodes.py | 90 --- src/compiler/nir/nir_opcodes_c.py | 4 +- 3 files changed, 52 insertions(+), 45 deletions(-) diff --git a/src/compiler/nir/nir.h b/src/

[Mesa-dev] [PATCH v3 19/44] nir/algebraic: add lowerings for ldexp with rounding modes

--- src/compiler/nir/nir_opt_algebraic.py | 70 +++ 1 file changed, 70 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 3800db1da20..3384c9c2e67 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++ b/src/comp

[Mesa-dev] [PATCH v3 17/44] nir/algebraic: disable inexact optimizations if SHADER_SIGNED_ZERO_INF_NAN_PRESERVE is enabled

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_algebraic.py | 13 - 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index fe9d1051e67..9aa1b1928b8 100644 --- a/src/compiler/nir/nir_

[Mesa-dev] [PATCH v3 08/44] util: added float to float16 conversions with RTZ and RTNE

Signed-off-by: Samuel Iglesias Gonsálvez --- src/util/half_float.c | 74 +++ src/util/half_float.h | 7 2 files changed, 81 insertions(+) diff --git a/src/util/half_float.c b/src/util/half_float.c index 63aec5c5c14..5fdcb20045b 100644 --- a/src/util/

[Mesa-dev] [PATCH v3 21/44] spirv/nir: add rounding mode support for fadd, fsub, fmul

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_alu.c | 28 +++- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 848fbbdb07c..881a9bab314 100644 --- a/src/compiler/spirv/vt

[Mesa-dev] [PATCH v3 22/44] spirv/nir: add rounding mode support for SpvOpVectorTimesScalar and SpvOpMatrixTimesScalar

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_alu.c | 24 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 881a9bab314..06320adf152 100644 --- a/src/compiler/spirv/vtn_al

[Mesa-dev] [PATCH v3 20/44] spirv/nir: add rounding mode support for floating-point conversions

v2: - Fixed bug in rounding modes for conversion ops, it was not considering the rounding mode of the destination data type. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 16 src/compiler/spirv/vtn_alu.c | 14 +- 2 files changed, 29 inse

[Mesa-dev] [PATCH v3 06/44] spirv/glsl450: fix atan2(x, x) case

If x < 0 -> atan2(x, x) = -3*pi/4. If x > 0 -> atan2(x, x) = pi/4. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index

[Mesa-dev] [PATCH v3 25/44] spirv/nir: add rounding mode support for GLSLstd450Modf opcode

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 17 ++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index e9b1b0b8fec..8128ed346af 100644 --- a/src/compiler/spirv/v

[Mesa-dev] [PATCH v3 07/44] spirv/glsl450: fix reflect(denorm, denorm) FTZ = 0.0 case

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index a6d2c5fdd07..b0092bcb2ad 100644 --- a/src/compiler/spirv/vtn_gl

[Mesa-dev] [PATCH v3 13/44] nir: add new ldexp opcodes taking into account rounding mode

According to Vulkan spec, the new execution modes affect only correctly rounded SPIR-V instructions, which is the case for ldexp. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/compiler/nir/nir_

[Mesa-dev] [PATCH v3 15/44] nir: add new ffract opcodes taking into account rounding mode

According to Vulkan spec, the new execution modes affect only correctly rounded SPIR-V instructions, which includes Fract. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_

[Mesa-dev] [PATCH v3 24/44] spirv/nir: add rounding mode support for FaceForward opcode

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 21 + 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index b62641f3db5..e9b1b0b8fec 100644 --- a/src/compiler/spi

[Mesa-dev] [PATCH v3 16/44] nir/constant_expressions: take into account rounding mode to convert from float to float16 destinations

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_constant_expressions.py | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_constant_expressions.py b/src/compiler/nir/nir_constant_expressions.py index e79590f8359..0b3da1b21ac

[Mesa-dev] [PATCH v3 18/44] nir/algebraic: add optimizations for fadd, fsub and fmul with rounding mode

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opt_algebraic.py | 73 +++ 1 file changed, 73 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 71c626e1b3f..3800db1da20 100644 --- a/src/compil

[Mesa-dev] [PATCH v3 09/44] util: add fp64 -> fp32 conversion support for RTNE and RTZ rounding modes

Signed-off-by: Samuel Iglesias Gonsálvez --- src/util/Makefile.sources | 2 + src/util/double.c | 197 ++ src/util/double.h | 46 + src/util/meson.build | 2 + 4 files changed, 247 insertions(+) create mode 100644 src/util/dou

[Mesa-dev] [PATCH v3 11/44] nir: add new floating point conversion opcodes taking into account rounding mode

It adds round-towards-zero and round-to-nearest-even opcodes for floating point conversions. According to Vulkan spec, the new execution modes affect only correctly rounded SPIR-V instructions, which includes these conversions. v2: - Move code to nir_opcodes.py (Connor) Signed-off-by: Samuel Igl

[Mesa-dev] [PATCH v3 29/44] nir: fix fmin/fmax support for doubles

Until now, it was using the floating point version of fmin/fmax, instead of the double version. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/

[Mesa-dev] [PATCH v3 27/44] nir: fix denorms in unpack_half_1x16()

According to VK_KHR_shader_float_controls: "Denormalized values obtained via unpacking an integer into a vector of values with smaller bit width and interpreting those values as floating-point numbers must: be flushed to zero, unless the entry point is declared with the code:DenormPreserve exec

[Mesa-dev] [PATCH v3 26/44] spirv/nir: add rounding mode support for GLSLstd450Fract opcode

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 8128ed346af..b6036cf876e 100644 --- a/src/compiler/spirv/vtn_glsl450.c

[Mesa-dev] [PATCH v3 31/44] i965/fs: add nir_op_f2f*_{rtne,rtz}

This way, we can implement its support later if SPIR-V supports it. Right now, the RTZ, RTNE support in SPIR-V in FPRoundingMode only applies to f2f16 conversions. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 4 1 file changed, 4 insertions(+) diff --git

[Mesa-dev] [PATCH v3 12/44] nir: add new fadd, fsub, fmul opcodes taking into account rounding mode

According to Vulkan spec, the new execution modes affect only correctly rounded SPIR-V instructions, which includes fadd, fsub and fmul. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_opcodes.py | 17 + 1 file changed, 17 insertions(+) diff --git a/src/compile

[Mesa-dev] [PATCH v3 28/44] nir: fix denorm flush-to-zero in sqrt's lowering at nir_lower_double_ops

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir_lower_double_ops.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_lower_double_ops.c b/src/compiler/nir/nir_lower_double_ops.c index 4d4cdf635ea..525f2d19dc7 100644 --- a/src/comp

[Mesa-dev] [PATCH v3 23/44] spirv/nir: add rounding mode support for GLSLstd450Ldexp

Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/spirv/vtn_glsl450.c | 20 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index b0092bcb2ad..b62641f3db5 100644 --- a/src/compiler/spir

[Mesa-dev] [PATCH v3 30/44] intel/nir: call nir_opt_constant_folding before brw_nir_apply_trig_workarounds

If we have fsin or fcos trigonometric operations with constant values as inputs, we will multiply the result by 0.7 in brw_nir_apply_trig_workarounds, making the result wrong. Running nir_opt_constant_folding before, we will calculate correctly the result for these trignometric ops. Signed-off

[Mesa-dev] [PATCH v3 40/44] i965/fs: remove brw_rounding_mode() and use brw_float_controls_mode() instead

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_eu.h | 4 --- src/intel/compiler/brw_eu_emit.c| 36 - src/intel/compiler/brw_fs_generator.cpp | 13 +++-- 3 files changed, 11 insertions(+), 42 deletions(-) diff --git a/src/intel

[Mesa-dev] [PATCH v3 35/44] i965/fs/generator: add support to set floating points modes in control register

v2: - Fix bug in defining BRW_CR0_FP_MODE_MASK. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_eu.h | 4 src/intel/compiler/brw_eu_defines.h | 10 ++ src/intel/compiler/brw_eu_emit.c| 26 + src/intel/compiler/brw_

[Mesa-dev] [PATCH v3 39/44] i965/fs: set rounding mode when emitting the respective fadd and fmul instructions

--- src/intel/compiler/brw_fs_nir.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index aab06a525bc..86ab8c48135 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@

[Mesa-dev] [PATCH v3 36/44] i965/fs: define emit_shader_float_controls_execution_mode() and aux functions

We need this function to emit code that setups the control register later with the defined execution mode for the shader. v2: - Fix bug in setting the default mode mask in brw_rnd_mode_from_nir() - Fix support for rounding modes in brw_rnd_mode_from_nir() Signed-off-by: Samuel Iglesias Gonsálvez

[Mesa-dev] [PATCH v3 38/44] i965/fs: set rounding mode when emitting affected conversion instructions

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 22 +- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 71e5a96e0a3..aab06a525bc 100644 --- a/src/intel/c

[Mesa-dev] [PATCH v3 33/44] i965/fs/nir: check that fdot*_{rtne, rtz} was properly lowered

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index ef1ed9b7f0a..9dacff9785b 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/i

[Mesa-dev] [PATCH v3 34/44] i965/fs/nir: add nir_op_unpack_half_2x16_split_*_flush_to_zero

The denorm mode is set in the control register, no need to do something else. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 9dacff97

[Mesa-dev] [PATCH v3 37/44] i965/fs: emit shader float controls execution modes as first instruction of shaders

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 809c7971c94..dfa6176340a 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compi

[Mesa-dev] [PATCH v3 32/44] i965/fs: add nir_op_ffract_{rtne, rtz} support

According to the PRMs: "The frc instruction computes, component-wise, the truncate-to-minus-infinity fractional values of src0 and stores the results in dst. The results, in the range of [0.0, 1.0], are the fractional portion of the source data. The result is in the range [0.0, 1.0] irrespective o

[Mesa-dev] [PATCH v3 43/44] anv: enable support for SPV_KHR_shader_float_controls capabilities

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index adc8bb4ddf5..1ee0e4d3e4e 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv

[Mesa-dev] [PATCH v3 41/44] i965/fs: add support for shader float control to remove_extra_rounding_modes()

The remove_extra_rounding_modes() optimization will remove duplicated rounding mode changes. v2: - Fix bug in the rounding mode change (Alejandro) v3: - Fix rounding modes. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs.cpp | 13 - 1 file changed, 12 inserti

[Mesa-dev] [PATCH v3 42/44] anv: add support for VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_device.c | 31 +++ 1 file changed, 31 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 6b272ecf558..3d5ffa641a0 100644 --- a/src/intel/vulkan/anv_device.c +

[Mesa-dev] [PATCH v3 44/44] anv: enable VK_KHR_shader_float_controls extension

Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/anv_extensions.py | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index defe263b2fb..fb8e9d593a3 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src/int

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Eero Tamminen changed: What|Removed |Added Depends on||108787 Referenced Bugs: https://bugs.

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Eero Tamminen changed: What|Removed |Added Depends on||108820 Referenced Bugs: https://bugs.

Re: [Mesa-dev] 10-bit fbconfigs break most video players using VAAPI+GLX

On 2019-02-05 11:30 p.m., Marek Olšák wrote: > Hi, > > Video players request fbconfigs with these attributes: > GLX_RED_SIZE = 8 > GLX_GREEN_SIZE = 8 > GLX_BLUE_SIZE = 8 > GLX_ALPHA_SIZE = 0 > > Note that the values specify MINIMUM required component sizes, not exact > sizes. 10-10-10-2 satisfies

Re: [Mesa-dev] [PATCH v3 12/44] nir: add new fadd, fsub, fmul opcodes taking into account rounding mode

On Wed, Feb 6, 2019 at 11:46 AM Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > According to Vulkan spec, the new execution modes affect only > correctly rounded SPIR-V instructions, which includes fadd, > fsub and fmul. > > Signed-off-by: Samuel Iglesias Gonsálvez > --- > src/compile

Re: [Mesa-dev] 10-bit fbconfigs break most video players using VAAPI+GLX

On 2/6/19 1:16 PM, Michel Dänzer wrote: On 2019-02-05 11:30 p.m., Marek Olšák wrote: Hi, Video players request fbconfigs with these attributes: GLX_RED_SIZE = 8 GLX_GREEN_SIZE = 8 GLX_BLUE_SIZE = 8 GLX_ALPHA_SIZE = 0 Note that the values specify MINIMUM required component sizes, not exact siz

[Mesa-dev] [PATCH] relnotes: Add documentation for newly supported extensions

EXT_sRGB_write_control and EXT_texture_sRGB_R8 are now supported on all drivers that support sRGB. Signed-off-by: Gert Wollny CC: --- docs/relnotes/19.0.0.html | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/relnotes/19.0.0.html b/docs/relnotes/19.0.0.html index 1b4edd7ce76..33b35ab8

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Eero Tamminen changed: What|Removed |Added Depends on||109055 Referenced Bugs: https://bugs.

Re: [Mesa-dev] [ANNOUNCE] mesa 19.0.0-rc

Hi, On 4.2.2019 14.41, Eero Tamminen wrote: On 2.2.2019 3.20, Mark Janes wrote: [...] These regressions all need to be added to the release tracker.  Thank you for reporting them. If that should track all the things regressed since previous 18.3 version was branched: --- tag

[Mesa-dev] [Bug 109565] CmdBindDescriptorSets gets confused about dynamic offsets

https://bugs.freedesktop.org/show_bug.cgi?id=109565 Bug ID: 109565 Summary: CmdBindDescriptorSets gets confused about dynamic offsets Product: Mesa Version: unspecified Hardware: Other OS: All St

[Mesa-dev] [Bug 109565] CmdBindDescriptorSets gets confused about dynamic offsets

https://bugs.freedesktop.org/show_bug.cgi?id=109565 --- Comment #1 from Jakub Okoński --- This is on 19.0.0-rc2 compiled with --buildtype=debug, but debug symbols are still missing? I'm not sure why that is the case. -- You are receiving this mail because: You are the QA Contact for the bug. Yo

Re: [Mesa-dev] [PATCH] egl/dri: de-duplicate dri2_load_driver*

On Tuesday, 2019-02-05 15:19:46 +, Emil Velikov wrote: > From: Emil Velikov > > The difference between the tree functions is the list of mandatory > driver extensions. Pass that as an argument to the common helper. > > Signed-off-by: Emil Velikov Pretty sure I also have this patch somewher

[Mesa-dev] [Bug 109565] CmdBindDescriptorSets gets confused about dynamic offsets

https://bugs.freedesktop.org/show_bug.cgi?id=109565 --- Comment #2 from Samuel Pitoiset --- Are you sure you use dynamic bindings correctly first? Can you share a link to your custom app? -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bu

[Mesa-dev] [Bug 109565] CmdBindDescriptorSets gets confused about dynamic offsets

https://bugs.freedesktop.org/show_bug.cgi?id=109565 --- Comment #3 from Jakub Okoński --- I'm not sure what you mean, I don't use any of the *_DYNAMIC variants of DescriptorType. This is how I define the layout of 2nd Descriptor Set I'm trying to bind in the failing call: https://github.com/farn

[Mesa-dev] [Bug 109565] CmdBindDescriptorSets gets confused about dynamic offsets

https://bugs.freedesktop.org/show_bug.cgi?id=109565 --- Comment #4 from Jakub Okoński --- If I try binding just the 2nd one, it does not crash and lets me submit that command buffer to the compute queue. The problem must be with the first set (called mvp_set in my app). It fails to bind in a grap

[Mesa-dev] [Bug 109565] CmdBindDescriptorSets gets confused about dynamic offsets

https://bugs.freedesktop.org/show_bug.cgi?id=109565 --- Comment #5 from Jakub Okoński --- So I've duplicated the binding of that set into two separate bindings, one for VERTEX stage, one for COMPUTE. And I updated them the same way: Thread 0, Frame 0: vkUpdateDescriptorSets(device, descriptorWri

Re: [Mesa-dev] [PATCH 4/6] glsl/linker: don't fail non static used inputs without matching outputs

On Wed, 2019-02-06 at 09:42 +1100, Timothy Arceri wrote: > On 6/2/19 1:11 am, Andres Gomez wrote: > > On Fri, 2019-02-01 at 18:37 -0500, Ilia Mirkin wrote: > > > On Fri, Feb 1, 2019 at 1:08 PM Andres Gomez wrote: > > > > If there is no Static Use of an input variable, the linker shouldn't > > > >

Re: [Mesa-dev] 10-bit fbconfigs break most video players using VAAPI+GLX

On Tue, 2019-02-05 at 17:30 -0500, Marek Olšák wrote: > If we expose 10-bit or 16-bit formats, a lot of software will be > broken. Any ideas how to get out of this rabbit hole? Use GLX_SGIX_visual_select_group to hide the depth-30 formats after the depth-24 ones. We're already doing this for simi

[Mesa-dev] [PATCH v2 4/6] glsl/linker: don't fail non static used inputs without matching outputs

If there is no Static Use of an input variable, the linker shouldn't fail whenever there is no defined matching output variable in the previous stage. From page 47 (page 51 of the PDF) of the GLSL 4.60 v.5 spec: " Only the input variables that are statically read need to be written by the p

Re: [Mesa-dev] 10-bit fbconfigs break most video players using VAAPI+GLX

On Wed, 2019-02-06 at 10:33 -0500, Adam Jackson wrote: > On Tue, 2019-02-05 at 17:30 -0500, Marek Olšák wrote: > > > If we expose 10-bit or 16-bit formats, a lot of software will be > > broken. Any ideas how to get out of this rabbit hole? > > Use GLX_SGIX_visual_select_group to hide the depth-30

Re: [Mesa-dev] 10-bit fbconfigs break most video players using VAAPI+GLX

On 2019-02-06 12:55 p.m., Tapani Pälli wrote: > On 2/6/19 1:16 PM, Michel Dänzer wrote: >> On 2019-02-05 11:30 p.m., Marek Olšák wrote: >>> Hi, >>> >>> Video players request fbconfigs with these attributes: >>> GLX_RED_SIZE = 8 >>> GLX_GREEN_SIZE = 8 >>> GLX_BLUE_SIZE = 8 >>> GLX_ALPHA_SIZE = 0 >>>

Re: [Mesa-dev] [PATCH 4/8] i965: Update the shadow miptree from the main to fake the ETC2 compression

On Sun, Feb 03, 2019 at 03:59:42PM +0200, Eleni Maria Stea wrote: > On Fri, 18 Jan 2019 17:09:03 -0800 > Nanley Chery wrote: > > > On Mon, Nov 19, 2018 at 10:54:08AM +0200, Eleni Maria Stea wrote: > [...] > > > + int img_d = smt->surf.logical_level0_px.depth; > > > > I don't think 3D ETC tex

Re: [Mesa-dev] [ANNOUNCE] mesa 19.0.0-rc1

Quoting Eero Tamminen (2019-02-04 04:41:12) > Hi, > > On 2.2.2019 3.20, Mark Janes wrote: > > Eero Tamminen writes: > >> On 31.1.2019 1.37, Dylan Baker wrote: > >>> This email announces the mesa 19.0 release candidate 1. I'll keep this > >>> email > >>> fairly brief since I'm already running a l

[Mesa-dev] [PATCH] freedreno: Fix meson build.

../src/gallium/drivers/freedreno/freedreno_resource.c: In function ‘fd_resource_create_with_modifiers’: ../src/gallium/drivers/freedreno/freedreno_resource.c:884:30: error: ‘DRM_FORMAT_MOD_QCOM_COMPRESSED’ undeclared (first use in this function) allow_ubwc = find_modifier(DRM_FORMAT_MOD_QCOM_C

[Mesa-dev] [Bug 109574] Blender 2.8

https://bugs.freedesktop.org/show_bug.cgi?id=109574 Bug ID: 109574 Summary: Blender 2.8 Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Pr

Re: [Mesa-dev] [PATCH v2 2/5] i965: Removed assertions from intel_miptree_map_etc

On Sun, Feb 03, 2019 at 03:07:33PM +0200, Eleni Maria Stea wrote: > The assertions that the GL_MAP_WRITE_BIT and GL_MAP_INVALIDATE_RANGE_BIT > in intel_miptree_map_etc will fail when the ETC miptree is mapped for > reading. As we are about to fix the GetCompressed* functions in the > following patc

[Mesa-dev] [PATCH v2 4/7] gallium/auxiliary/vl: Add compute shader to support video compositor render

Add compute shader to support video compositor render. Signed-off-by: James Zhu --- src/gallium/auxiliary/Makefile.sources | 2 + src/gallium/auxiliary/meson.build | 2 + src/gallium/auxiliary/vl/vl_compositor.h| 1 + src/gallium/auxiliary/vl/vl_compositor_cs.c | 408 +++

[Mesa-dev] [PATCH v2 1/7] gallium/auxiliary/vl: Move dirty define to header file

Move dirty define to header file to share with compute shader. Signed-off-by: James Zhu --- src/gallium/auxiliary/vl/vl_compositor.c | 15 ++- src/gallium/auxiliary/vl/vl_compositor.h | 2 ++ 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/src/gallium/auxiliary/vl/vl_

[Mesa-dev] [PATCH v2 7/7] gallium/auxiliary/vl: Add video compute shader render

Add video compute shader render. export CS_COMPOSITOR_RENDER=true to enable video compute shader render. Signed-off-by: James Zhu --- src/gallium/auxiliary/vl/vl_compositor.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/vl/vl_compositor.c b/src/

[Mesa-dev] [PATCH v2 0/7] Add compute shader support on video compositor render

V2: Split vl_compositor graphic shaders from vl_compositor API replace compute_shader_sub_pic with compute_shader_rgba Add VL_COMPOSITOR prefix in front of dirty define replace backslashes in the commit title with forward slashes James Zhu (7): gallium/auxiliary/vl: Move dirty define to

[Mesa-dev] [PATCH v2 3/7] gallium/auxiliary/vl: Increase csc_matrix size

Increase csc_matrix size to store more constants for compute shader. Signed-off-by: James Zhu --- src/gallium/auxiliary/vl/vl_compositor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/vl/vl_compositor.c b/src/gallium/auxiliary/vl/vl_compositor.c inde

[Mesa-dev] [PATCH v2 6/7] gallium/auxiliary/vl: Add debug option CS_COMPOSITOR_RENDER

Add debug option CS_COMPOSITOR_RENDER to enable/diable video compositor compute shader render through system environment Signed-off-by: James Zhu --- src/gallium/auxiliary/vl/vl_compositor.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/auxiliary/vl/vl_compositor.c b/src/g

[Mesa-dev] [PATCH v2 5/7] gallium/auxiliary/vl: Add compute shader initilization, assign and cleanup

Add compute shader initilization, assign and cleanup in vl_compositor API. Signed-off-by: James Zhu --- src/gallium/auxiliary/vl/vl_compositor.c | 31 ++- src/gallium/auxiliary/vl/vl_compositor.h | 3 +++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a

[Mesa-dev] [PATCH v2 2/7] gallium/auxiliary/vl: Split vl_compositor graphic shaders from vl_compositor API

Split vl_compositor graphic shaders from vl_compositor API in order to share vl_compositor API with vl_compositor compute shader later. Signed-off-by: James Zhu --- src/gallium/auxiliary/Makefile.sources | 2 + src/gallium/auxiliary/meson.build| 2 + src/gallium/auxiliary/v

Re: [Mesa-dev] [PATCH v2] kmsro: Move DRM entrypoints to shared block

Alyssa Rosenzweig writes: > As kmsro allows an essentially mix-and-match hodgepodge of display > drivers and renderonly GPUs, it doesn't make sense to couple the display > driver entrypoint definition with the driver. Instead, we move *all* > kmsro entrypoints to a shared kmsro block at the end (

Re: [Mesa-dev] [PATCH v2 5/5] i965: Enabled the OES_copy_image extension on Gen 7 GPUs

On Sun, Feb 03, 2019 at 03:07:36PM +0200, Eleni Maria Stea wrote: > OES_copy_image extension was disabled on Gen7 due to the lack of support > for ETC2 images. Enabled it back. (Kenneth Graunke) > --- > src/mesa/drivers/dri/i965/intel_extensions.c | 18 ++ > 1 file changed, 14 inse

[Mesa-dev] [Bug 109535] [Tracker] Mesa 19.0 release tracker

https://bugs.freedesktop.org/show_bug.cgi?id=109535 Timothy Arceri changed: What|Removed |Added Depends on||109561 Referenced Bugs: https://bugs

Re: [Mesa-dev] [PATCH v2 4/6] glsl/linker: don't fail non static used inputs without matching outputs

Before reviewing this can we get a piglit test for the following scenario Two "program" objects say: 1. vs->gs 2. fs Where the interface between vs and gs has a used input that doesn't exist in the vs. The test should fail validation, the idea being the test would have failed on your v1 of th

[Mesa-dev] [PATCH 2/2] radeonsi: fix EXPLICIT_FLUSH for flush offsets > 0

From: Marek Olšák Cc: 18.3 19.0 --- src/gallium/drivers/radeonsi/si_buffer.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c index bac561de2cb..c01118ce96a 100644 --- a/src/gallium/dr

[Mesa-dev] [PATCH 1/2] gallium/u_threaded: fix EXPLICIT_FLUSH for flush offsets > 0

From: Marek Olšák Cc: 18.3 19.0 --- src/gallium/auxiliary/util/u_threaded_context.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/util/u_threaded_context.c b/src/gallium/auxiliary/util/u_threaded_context.c index 8e3bceae18d..b596c322918 100644 ---

[Mesa-dev] [PATCH 3/6] winsys/amdgpu: use a separate fence list for syncobjs

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 31 ++- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 + 2 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

[Mesa-dev] [PATCH 1/6] winsys/amdgpu: don't drop manually added fence dependencies

From: Marek Olšák wow, it's hard to believe that fence and syncobjs dependencies were ignored. Cc: 18.3 19.0 --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

[Mesa-dev] [PATCH 4/6] winsys/amdgpu: remove occurence of INDIRECT_BUFFER_CONST

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index a059a3958d4..0d2dab88317 100644 --- a/src/gallium/winsys/amdgpu/drm/a

[Mesa-dev] [PATCH 2/6] winsys/amdgpu: unify fence list code

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 86 +-- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 15 ++-- 2 files changed, 42 insertions(+), 59 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs

[Mesa-dev] [PATCH 5/6] winsys/amdgpu: clean up IB buffer size computation

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c index 0d2dab88317..b3dedef3d73 100644 --- a/src/gallium/winsys/a

[Mesa-dev] [PATCH 6/6] winsys/amdgpu: cs_check_space sets the minimum IB size for future IBs

From: Marek Olšák --- src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 18 -- src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 7 +++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 Bug ID: 109575 Summary: Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 --- Comment #1 from LunarG --- Possibly related to bug https://bugs.freedesktop.org/show_bug.cgi?id=109543 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___

Re: [Mesa-dev] last call for autotools

I have a patch series pending review to add support for pkg_config_path as a -Doption (or in your native/cross file, if you like that better). Quoting Tapani Pälli (2019-02-05 22:20:14) > > > On 2/5/19 8:20 PM, Marek Olšák wrote: > > PKG_CONFIG_PATH still seems to be forgotten by meson. Is there

[Mesa-dev] [PATCH] intel/fs: Use enumerated array assignments in fb read TXF setup

It's more clear and means we don't have to update the array every time we add an optional texture instruction argument --- src/intel/compiler/brw_fs_nir.cpp | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/br

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 --- Comment #2 from Bas Nieuwenhuizen --- Say I have a computer with similar GPU sitting around just for testing. What would be the way to get to a similar software setup? What distro do you use, what is your compiler, where did your kernel com

[Mesa-dev] [Bug 109575] Mesa-19.0.0-rc1 : Computer Crashes trying to run anything Vulkan

https://bugs.freedesktop.org/show_bug.cgi?id=109575 --- Comment #3 from LunarG --- --Distro-- Ubuntu 16.04 --Kernel from Ubuntu's PPA-- https://kernel.ubuntu.com/~kernel-ppa/mainline/v4.10/ --GCC version-- gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609 Compiled Mesa using autotools with th

Re: [Mesa-dev] [PATCH] intel/fs: Use enumerated array assignments in fb read TXF setup

This patch is Reviewed-by: Caio Marcelo de Oliveira Filho On Wed, Feb 06, 2019 at 04:43:00PM -0600, Jason Ekstrand wrote: > It's more clear and means we don't have to update the array every time > we add an optional texture instruction argument > --- > src/intel/compiler/brw_fs_nir.cpp | 14 ++

[Mesa-dev] [PATCH 2/4] gallium/u_threaded: always unmap const_uploader

From: Marek Olšák radeonsi will require this. It's a no-op for drivers supporting persistent mappings. --- src/gallium/auxiliary/util/u_threaded_context.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/auxiliary/util/u_threaded_context.c b/src/gallium/auxiliary/util/u_threaded_

[Mesa-dev] [PATCH 3/4] gallium/u_upload_mgr: allow use of FLUSH_EXPLICIT with persistent mappings

From: Marek Olšák for radeonsi --- src/gallium/auxiliary/util/u_upload_mgr.c | 33 ++- src/gallium/auxiliary/util/u_upload_mgr.h | 4 +++ 2 files changed, 31 insertions(+), 6 deletions(-) diff --git a/src/gallium/auxiliary/util/u_upload_mgr.c b/src/gallium/auxiliary/util/u

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