https://bugs.freedesktop.org/show_bug.cgi?id=108355
Michel Dänzer changed:
What|Removed |Added
Attachment #142059|text/x-log |text/plain
mime type|
https://bugs.freedesktop.org/show_bug.cgi?id=108355
--- Comment #6 from Michel Dänzer ---
Does it still happen with xf86-video-amdgpu 18.1.0?
Does amdgpu.dc=0 on the kernel command line avoid the problem?
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Reviewed-by: Iago Toral Quiroga
On Wed, 2018-10-17 at 14:49 +1100, Timothy Arceri wrote:
> For example:
>
>vec1 32 ssa_386 = feq ssa_333.x, ssa_6
>vec1 32 ssa_387 = feq ssa_333.x, ssa_2
>vec1 32 ssa_391 = bcsel ssa_387, ssa_388, ssa_324
>vec1 32 ssa_396 = bcsel ssa_386, ssa_324,
https://bugs.freedesktop.org/show_bug.cgi?id=108105
--- Comment #13 from Samuel Pitoiset ---
Patch available here https://reviews.llvm.org/D53359
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https://bugs.freedesktop.org/show_bug.cgi?id=104302
--- Comment #22 from Samuel Pitoiset ---
Patch available here https://reviews.llvm.org/D53359
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On Wed, Oct 17, 2018 at 5:49 AM Timothy Arceri wrote:
>
> For example:
>
>vec1 32 ssa_386 = feq ssa_333.x, ssa_6
>vec1 32 ssa_387 = feq ssa_333.x, ssa_2
>vec1 32 ssa_391 = bcsel ssa_387, ssa_388, ssa_324
>vec1 32 ssa_396 = bcsel ssa_386, ssa_324, ssa_391
>
> Can be simplified to:
>
SIMD16 instructions need to have additional interferences to prevent
source / destination hazards when the source and destination registers
are off by one register.
While we already have code to handle this, it was only running for SIMD16
dispatches, however, we can have SIDM16 instructions in a S
On 17/10/18 8:49 pm, Bas Nieuwenhuizen wrote:
On Wed, Oct 17, 2018 at 5:49 AM Timothy Arceri wrote:
For example:
vec1 32 ssa_386 = feq ssa_333.x, ssa_6
vec1 32 ssa_387 = feq ssa_333.x, ssa_2
vec1 32 ssa_391 = bcsel ssa_387, ssa_388, ssa_324
vec1 32 ssa_396 = bcsel ssa_386, ssa
This patch never landed in git, is that intentional?
On Mon, 1 Oct 2018 at 17:46, Jason Ekstrand wrote:
> On Sun, Sep 30, 2018 at 1:04 PM Bas Nieuwenhuizen
> wrote:
>
>> ---
>> src/amd/vulkan/radv_device.c | 27 +++
>> src/amd/vulkan/radv_extensions.py | 1 +
>> 2
This series implement VK_KHR_draw_indirect_count and
VK_EXT_conditional_rendering extensions.
They are implemented together because they are highly interweaved.
There are already tests in VK_CTS for VK_KHR_draw_indirect_count and I made a
pull request with
the tests for VK_EXT_conditional_render
Signed-off-by: Danylo Piliaiev
---
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/genX_cmd_buffer.c | 155 +
2 files changed, 156 insertions(+)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index d4915c9501..7f44da
Without MI_MATH we are forced to load MI_PREDICATE_SRC0
from memory on every predicate emission.
Signed-off-by: Danylo Piliaiev
---
src/intel/vulkan/anv_extensions.py | 2 +-
src/intel/vulkan/genX_cmd_buffer.c | 12 ++--
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/sr
Conditional rendering affects next functions:
- vkCmdDraw, vkCmdDrawIndexed, vkCmdDrawIndirect, vkCmdDrawIndexedIndirect
- vkCmdDrawIndirectCountKHR, vkCmdDrawIndexedIndirectCountKHR
- vkCmdDispatch, vkCmdDispatchIndirect, vkCmdDispatchBase
- vkCmdClearAttachments
To reduce readings from the memor
On Tue, 16 Oct 2018 at 08:17, Peter Hutterer wrote:
> On Mon, Oct 15, 2018 at 10:49:24AM -0400, Harry Wentland wrote:
> > + \item Support free and open source projects through the
> > freedesktop.org
> > + infrastructure. For projects outside the scope of item (\ref{1})
> > support
> > +
https://bugs.freedesktop.org/show_bug.cgi?id=100960
--- Comment #17 from Sergii Romantsov ---
Hello, Fabian.
Unfortunately, probably, no one will be interest in that fix in the Mesa so
much.
The reason: actually issue is in the game. Specification doesn't specify exact
way how to handle it. So a
On Wed, Oct 17, 2018 at 2:05 PM Daniel Stone wrote:
>
> On Tue, 16 Oct 2018 at 08:17, Peter Hutterer wrote:
> > On Mon, Oct 15, 2018 at 10:49:24AM -0400, Harry Wentland wrote:
> > > + \item Support free and open source projects through the
> > > freedesktop.org
> > > + infrastructure. Fo
Needs to specify nondraw when creating a batch through
fd_bc_alloc_batch since it'd better create a batch through
it rather than fd_batch_create.
---
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c | 2 +-
src/gallium/drivers/freedreno/freedreno_batch_cache.c | 6 +++---
src/gallium/drivers/
Needs to allocate batches from the cache so that it could
get a valid index and make resource dependancy tracking right.
In addition this fixes assertion on debug build since the commit
1a40faa8 landed.
---
src/gallium/drivers/freedreno/freedreno_draw.c | 3 ++-
1 file changed, 2 insertions(+), 1
On 2018-10-07 9:05 a.m., Marek Olšák wrote:
> From: Marek Olšák
>
> Fast color clears should be much faster. Also, fast color clears on
> evicted buffers should be 200x faster on GFX8 and older.
Nice! Unfortunately, this broke clover with radeonsi. Everything using
OpenCL seems to hang, see e.g.
The modeline was missing a ‘:’ after the tab-width and Emacs was
complaining every time you open a file. This patch was made with:
sed -ri '1 s/; tab-width ([0-9])/; tab-width: \1/' \
$(find -name \*.\[ch\] -exec grep -l -- '-\*- mode:' {} \+)
---
src/gallium/drivers/freedreno/a2xx/fd2_blend.
On Wednesday, 2018-10-17 15:48:41 +0200, Neil Roberts wrote:
> The modeline was missing a ‘:’ after the tab-width and Emacs was
> complaining every time you open a file. This patch was made with:
>
> sed -ri '1 s/; tab-width ([0-9])/; tab-width: \1/' \
> $(find -name \*.\[ch\] -exec grep -l --
Signed-off-by: Danylo Piliaiev
---
src/intel/tools/intel_sanitize_gpu.c | 38 +++-
1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/src/intel/tools/intel_sanitize_gpu.c
b/src/intel/tools/intel_sanitize_gpu.c
index 9b49b0bbf2..36c4725a2f 100644
--- a/src/int
On Wed, 3 Oct 2018 at 15:08, Emil Velikov wrote:
>
> Hi all,
>
> This re-spin of the series includes:
> - correct flipped asserts
> - cosmetic wording/comment fixes
> - drop EGL_EXT_platform_device patches (swrast is broken)
> - add the EGL_MESA_device_software spec patch
>
> At this point we
Eric Engestrom writes:
> You might want to remove these instead, and use the .editorconfig [1]
> already present at src/gallium/drivers/freedreno/.editorconfig This is
> much easier to maintain than per-files settings ;)
Either fixing it or removing it is fine by me. I now notice there is a
.dir
On Wed, Oct 17, 2018 at 12:14 AM Keith Packard wrote:
> Jason Ekstrand writes:
>
> > Doing all of the CPU sampling on one side or the other of the GPU
> sampling
> > would probably reduce our window.
>
> True, although as I said, it's taking several µs to get through the
> loop, and the gpu cloc
The .dir-locals.el had the wrong name for the truthy value so it
wasn’t setting indent-tabs-mode.
---
src/gallium/drivers/freedreno/.dir-locals.el | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/.dir-locals.el
b/src/gallium/drivers/freedreno/.dir-
These are not necessary because the corresponding settings are set via
the .dir-locals.el file anyway. Most of them were missing a ‘:’ after
“tab-width” which was making Emacs display an annoying warning
whenever you open the file.
This patch was made with:
sed -ri '/-\*- mode:/,/^$/d' \
$(fi
On Wed, Oct 17, 2018 at 06:08:34PM +0300, Danylo Piliaiev wrote:
> Signed-off-by: Danylo Piliaiev
> ---
> src/intel/tools/intel_sanitize_gpu.c | 38 +++-
> 1 file changed, 20 insertions(+), 18 deletions(-)
>
> diff --git a/src/intel/tools/intel_sanitize_gpu.c
> b/src/int
From: Marek Olšák
Cc: 18.1 18.2
---
src/gallium/drivers/radeonsi/si_state_draw.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 83eb646b791..612ca910cb9 100644
---
From: Marek Olšák
This fixes dEQP-GLES2.functional.rasterization.limits.points.
Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314
---
src/gallium/drivers/radeonsi/si_get.c | 5 +++--
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 2 +-
3 files change
Are you sure? It works fine for me... I'm not against fixing it to be
"t", but the current contents definitely worked fine for me. (As I
recall, I may be the one who checked this file in.)
On Wed, Oct 17, 2018 at 11:38 AM Neil Roberts wrote:
>
> The .dir-locals.el had the wrong name for the truthy
From: Gert Wollny
Dear all,
this series adds the basic plumbing for EXT_sRGB_write_control and enables it
for some drivers.
Since this is the first time I add an extension I'd ask reviews this to take a
specific look at the first patch.
One thing I left out therefore, is to enable this exten
From: Gert Wollny
This GLES extension gives the applications the control over deciding whether
the conversion from linear space to sRGB is necessary by enabling or
disabling this conversion at framebuffer write or blending time just
like it is possible for desktop GL.
Signed-off-by: Gert Wollny
From: Gert Wollny
Enables and passes on i965:
dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_enabled*
Signed-off-by: Gert Wollny
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
From: Gert Wollny
With this patch the extension EXT_sRGB_write_control is enabled for
gallium drivers that support sRGB formats as render targets.
Tested (and pass) on r600(evergreen) and softpipe:
dEQP-GLES31.functional.fbo.srgb_write_control.framebuffer_srgb_enabled*
with "MESA_GLES_VERSIO
Can you test the attached patch?
Marek
On Wed, Oct 17, 2018 at 9:31 AM Michel Dänzer wrote:
> On 2018-10-07 9:05 a.m., Marek Olšák wrote:
> > From: Marek Olšák
> >
> > Fast color clears should be much faster. Also, fast color clears on
> > evicted buffers should be 200x faster on GFX8 and olde
Ilia Mirkin writes:
> Are you sure? It works fine for me... I'm not against fixing it to be
> "t", but the current contents definitely worked fine for me. (As I
> recall, I may be the one who checked this file in.)
Yes, I’m sure. If you type “true” and then do C-x C-e to evaluate it
then Emacs g
Offers three clocks, device, clock monotonic and clock monotonic
raw. Could use some kernel support to reduce the deviation between
clock values.
v2:
Ensure deviation is at least as big as the GPU time interval.
v3:
Set device->lost when returning DEVICE_LOST.
Use MAX2 and
On Wed, Oct 17, 2018 at 12:38 PM Gert Wollny wrote:
>
> From: Gert Wollny
>
> This GLES extension gives the applications the control over deciding whether
> the conversion from linear space to sRGB is necessary by enabling or
> disabling this conversion at framebuffer write or blending time just
Some of the .dir-locals.el had the wrong name for the truthy value so
it wasn’t setting indent-tabs-mode.
---
src/gallium/drivers/freedreno/.dir-locals.el | 2 +-
src/gallium/drivers/r600/.dir-locals.el | 2 +-
src/gallium/drivers/radeon/.dir-locals.el| 2 +-
src/gallium/drivers/radeonsi/
On Wed, Oct 17, 2018 at 12:45 PM Neil Roberts wrote:
>
> Ilia Mirkin writes:
>
> > Are you sure? It works fine for me... I'm not against fixing it to be
> > "t", but the current contents definitely worked fine for me. (As I
> > recall, I may be the one who checked this file in.)
>
> Yes, I’m sure
Reviewed-by: Ilia Mirkin
On Wed, Oct 17, 2018 at 12:51 PM Neil Roberts wrote:
>
> Some of the .dir-locals.el had the wrong name for the truthy value so
> it wasn’t setting indent-tabs-mode.
> ---
> src/gallium/drivers/freedreno/.dir-locals.el | 2 +-
> src/gallium/drivers/r600/.dir-locals.el
On Wed, Oct 17, 2018 at 12:39 PM Gert Wollny wrote:
>
> From: Gert Wollny
>
> With this patch the extension EXT_sRGB_write_control is enabled for
> gallium drivers that support sRGB formats as render targets.
>
> Tested (and pass) on r600(evergreen) and softpipe:
>
> dEQP-GLES31.functional.fbo.
On Wed, Oct 17, 2018 at 12:49 PM Ilia Mirkin wrote:
> On Wed, Oct 17, 2018 at 12:38 PM Gert Wollny wrote:
> > diff --git a/src/mesa/main/extensions_table.h
> > b/src/mesa/main/extensions_table.h
> > index 09bf923bd0..1185156f23 100644
> > --- a/src/mesa/main/extensions_table.h
> > +++ b/src/mesa
> On Wed, Oct 17, 2018 at 12:45 PM Neil Roberts wrote:
>
>> I wonder if you have something else in your setup that is setting it?
Ilia Mirkin writes:
> Perhaps. It's the default, right?
It is the default but the toplevel .dir-locals.el sets it to nil. These
lower-level files are trying to ove
I like it
Reviewed-by: Jason Ekstrand
On Wed, Oct 17, 2018 at 11:49 AM Keith Packard wrote:
> Offers three clocks, device, clock monotonic and clock monotonic
> raw. Could use some kernel support to reduce the deviation between
> clock values.
>
> v2:
> Ensure deviation is at least as
Dear all,
we are looking into doing a CI for virglrenderer that also runs a
subset of the GLES dEQP, and in order to be able to run this also in
gitlab.fd.o we were looking into the available gallium software
renderers. Inital tests by just running the dEQP-GLES2 were quite
successful in the sens
Am Mittwoch, den 17.10.2018, 12:56 -0400 schrieb Ilia Mirkin:
> On Wed, Oct 17, 2018 at 12:39 PM Gert Wollny
> wrote:
> >
> > From: Gert Wollny
> >
> > With this patch the extension EXT_sRGB_write_control is enabled for
> > gallium drivers that support sRGB formats as render targets.
> >
> > T
Jason Ekstrand writes:
> I like it
When the comments are longer than the code, you know you're done?
--
-keith
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Tested-by: Jakob Bornecrantz
On Wed, Oct 17, 2018 at 5:29 PM Marek Olšák wrote:
>
> From: Marek Olšák
>
> Cc: 18.1 18.2
> ---
> src/gallium/drivers/radeonsi/si_state_draw.c | 10 --
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state
Tested-by: Jakob Bornecrantz
On Wed, Oct 17, 2018 at 5:29 PM Marek Olšák wrote:
>
> From: Marek Olšák
>
> This fixes dEQP-GLES2.functional.rasterization.limits.points.
> Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314
> ---
> src/gallium/drivers/radeonsi/si_get.c | 5 +++--
> src/gallium/
On Wednesday, 2018-10-17 17:25:22 +0200, Neil Roberts wrote:
> Eric Engestrom writes:
>
> > You might want to remove these instead, and use the .editorconfig [1]
> > already present at src/gallium/drivers/freedreno/.editorconfig This is
> > much easier to maintain than per-files settings ;)
>
>
Eric Engestrom writes:
> That's absolutely fair :)
>
> I wanted to ack your patch earlier, since fixing it is good regardless,
> but freedreno isn't my area so I didn't feel comfortable doing so;
> I changed my mind in the mean time though, so here you go :P
> Acked-by: Eric Engestrom
>
> You ha
From: Connor Abbott
Shader-db results on Haswell:
total instructions in shared programs: 2180337 -> 2154080 (-1.20%)
instructions in affected programs: 959766 -> 933509 (-2.74%)
helped: 5653
HURT: 2560
total cycles in shared programs: 12339326 -> 12307102 (-0.26%)
cycles
The num_components value passed into get_mul_for_src is used to only
compose the parts of the swizzle that we know will be used so we don't
compose invalid swizzle components. However, we had a bug where we
passed the number of components of the add all the way through. For the
given source, we n
From: Connor Abbott
This effectively does the opposite of nir_lower_alus_to_scalar, trying
to combine per-component ALU operations with the same sources but
different swizzles into one larger ALU operation. It uses a similar
model as CSE, where we do a depth-first approach and keep around a hash
This is primarily a fix for the stable branch as it is still packaged
with LLVM 5 libs. This fixes a compile error if a user tries to build
with LLVM 6+ from an 18.2.x release tarball
Alok Hota (1):
swr/rast: ignore CreateElementUnorderedAtomicMemCpy
.../drivers/swr/rasterizer/codegen/gen_llvm
This function's API changed between LLVM 5 and 6. Compile errors occur
when building with LLVM 6+ if LLVM 5 was used for a dist tarball
---
.../drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/r
From: Boyuan Zhang
VCN jpeg requires new hw ip
Signed-off-by: Boyuan Zhang
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 520948b051..5fd7d8510d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -74,7 +74,7 @@ AC_SUBST([OPEN
From: Boyuan Zhang
VCN jpeg requires new hw ip
Signed-off-by: Boyuan Zhang
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 002ce35a60..35e3e934a3 100644
--- a/meson.build
+++ b/meson.build
@@ -1108,7 +1108,7 @@ dep_libdrm_etna
From: Boyuan Zhang
Move radeon_decoder definition from "radeon_vcn_dec.c" to "radeon_vcn_dec.h",
so that it can be included by other files later.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 31
src/gallium/drivers/rad
From: Boyuan Zhang
Add a new ring type for vcn jpeg.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_winsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
ind
From: Boyuan Zhang
Add VCN Jpeg decode interfaces and register defines.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vcn_dec.h | 90 +
1 file changed, 90 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.h
b/sr
From: Boyuan Zhang
Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/ra
From: Boyuan Zhang
Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 13 +-
src/gallium/state_trackers/va/picture_mjpeg.c | 142 ++
src/
From: Boyuan Zhang
Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg
specific cmd sending function in end_frame call.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 21 ++--
src/gallium/drivers/radeon/radeon_vcn_dec.h
From: Boyuan Zhang
Use function pointer for sending cmd in end_frame call. By doing this, we can
assign different cmd sending logics for Jpeg decode later.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 29 +++--
src/gallium/
From: Boyuan Zhang
Implement jpeg bitstream buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.
Signed-off-by: Boyuan Zhang
Acked-by: Leo Liu
---
.../drivers/radeon/radeon_vcn_dec_jpeg.c | 46 ++-
1 file changed, 45 insertions(+),
From: Boyuan Zhang
Move the previous get_mjpeg_slice_heaeder function and eoi from
"radeon/vcn" to "st/va".
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_uvd.c | 157
1 file changed, 157 deletions(-)
diff --git a/src/gallium/d
From: Boyuan Zhang
Implement jpeg target buffer cmd by programming registers directly,
since there is no firmware for VCN Jpeg decode.
Signed-off-by: Boyuan Zhang
Acked-by: Leo Liu
---
.../drivers/radeon/radeon_vcn_dec_jpeg.c | 73 ++-
1 file changed, 72 insertions(+), 1
From: Boyuan Zhang
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/amd/common/ac_gpu_info.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 766ad83547..8c50738c3f 100644
--- a/src/amd
From: Boyuan Zhang
Add vcn jpeg cs support, align cs by no-op.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgp
From: Boyuan Zhang
Enable vcn jpeg decode for raven.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeonsi/si_get.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_get.c
b/src/gallium/drivers/radeonsi/si_get.c
index a87cb3cbc8
https://bugs.freedesktop.org/show_bug.cgi?id=107765
--- Comment #13 from farmboy0+freedesk...@googlemail.com ---
Can you tell me what settings you use?
Do you use a 64 bit prefix?
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https://bugs.freedesktop.org/show_bug.cgi?id=108355
Hadrien Nilsson changed:
What|Removed |Added
Component|Drivers/Gallium/softpipe|Drivers/Gallium/swr
--- Comment #7 fr
Reviewed-by: Bruce Cherniak
> On Oct 17, 2018, at 1:51 PM, Alok Hota wrote:
>
> This function's API changed between LLVM 5 and 6. Compile errors occur
> when building with LLVM 6+ if LLVM 5 was used for a dist tarball
> ---
> .../drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py | 3 +
We already have wsi_device and we know the instance allocator at
wsi_device_init time so there's no need to pass it into the physical
device queries. This also fixes a memory allocation domain bug that can
occur if CreateSwapchain gets called prior to any queries (not likely)
in which case the cac
This got missed during 1.1 enabling because it was defined as an
interaction between device groups and WSI and it wasn't obvious it was
in the delta.
The idea behind it is that it's supposed to provide a hint to the
application in a multi-GPU setup to indicate which regions of the screen
are being
Am 17.10.18 um 19:15 schrieb Gert Wollny:
> Dear all,
>
> we are looking into doing a CI for virglrenderer that also runs a
> subset of the GLES dEQP, and in order to be able to run this also in
> gitlab.fd.o we were looking into the available gallium software
> renderers. Inital tests by just ru
This function's API changed between LLVM 5 and 6. Compile errors occur
when building with LLVM 6+ if LLVM 5 was used for a dist tarball
CC:
---
.../drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers
This patch fixes a compile error resulting from a function whose API
changed between LLVM versions 5 and 6. I sent this to mesa-dev, but it's
primarly a fix for the stable branch as it affects releases with LLVM
5-based codegen.
v2: included mesa-stable cc
Alok Hota (1):
swr/rast: ignore Create
Totals from affected shaders:
SGPRS: 2856 -> 2856 (0.00 %)
VGPRS: 3236 -> 3248 (0.37 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 236560 -> 233548 (-1.27 %) bytes
LDS: 0 -> 0 (0.00 %
Reviewed-by: Bas Nieuwenhuizen
On Wed, Oct 17, 2018 at 6:49 PM Keith Packard wrote:
>
> Offers three clocks, device, clock monotonic and clock monotonic
> raw. Could use some kernel support to reduce the deviation between
> clock values.
>
> v2:
> Ensure deviation is at least as big as th
On Thu, Oct 18, 2018 at 12:04 AM Timothy Arceri wrote:
>
> Totals from affected shaders:
> SGPRS: 2856 -> 2856 (0.00 %)
> VGPRS: 3236 -> 3248 (0.37 %)
> Spilled SGPRs: 0 -> 0 (0.00 %)
> Spilled VGPRs: 0 -> 0 (0.00 %)
> Private memory VGPRs: 0 -> 0 (0.00 %)
> Scratch size: 0 -> 0 (0.00 %) dwords pe
Totals from affected shaders:
SGPRS: 1112 -> 1112 (0.00 %)
VGPRS: 1492 -> 1196 (-19.84 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 112172 -> 101316 (-9.68 %) bytes
LDS: 0 -> 0 (0.00
On 18/10/18 9:51 am, Bas Nieuwenhuizen wrote:
On Thu, Oct 18, 2018 at 12:04 AM Timothy Arceri wrote:
Totals from affected shaders:
SGPRS: 2856 -> 2856 (0.00 %)
VGPRS: 3236 -> 3248 (0.37 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scrat
Reviewed-by: Bas Nieuwenhuizen
On Thu, Oct 18, 2018 at 1:00 AM Timothy Arceri wrote:
>
> Totals from affected shaders:
> SGPRS: 1112 -> 1112 (0.00 %)
> VGPRS: 1492 -> 1196 (-19.84 %)
> Spilled SGPRs: 0 -> 0 (0.00 %)
> Spilled VGPRs: 0 -> 0 (0.00 %)
> Private memory VGPRs: 0 -> 0 (0.00 %)
> Scratc
For full effect, you want to also enable shrink_vec_var_arrays and
split_array_vars
On Wed, Oct 17, 2018 at 6:00 PM Timothy Arceri
wrote:
> Totals from affected shaders:
> SGPRS: 1112 -> 1112 (0.00 %)
> VGPRS: 1492 -> 1196 (-19.84 %)
> Spilled SGPRs: 0 -> 0 (0.00 %)
> Spilled VGPRs: 0 -> 0 (0.00
and split_struct_vars while you're at it
On Wed, Oct 17, 2018 at 6:15 PM Jason Ekstrand wrote:
> For full effect, you want to also enable shrink_vec_var_arrays and
> split_array_vars
>
> On Wed, Oct 17, 2018 at 6:00 PM Timothy Arceri
> wrote:
>
>> Totals from affected shaders:
>> SGPRS: 1112 ->
We call in the opt loop in case another pass results in an
array with indirect access being turned into direct access.
Totals from affected shaders:
SGPRS: 512 -> 496 (-3.12 %)
VGPRS: 456 -> 452 (-0.88 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0
Totals from affected shaders:
SGPRS: 1096 -> 1096 (0.00 %)
VGPRS: 1192 -> 1056 (-11.41 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 100940 -> 94384 (-6.49 %) bytes
LDS: 0 -> 0 (0.00
Reviewed-by: Bas Nieuwenhuizen
for the series.
I wonder what the perf diff is for tessellation. See e.g.
https://github.com/doitsujin/dxvk/issues/645 for a game where
tessellation is hitting us hard.
On Thu, Oct 18, 2018 at 1:28 AM Timothy Arceri wrote:
>
> Totals from affected shaders:
> SGPRS
GREAT work Marek!
Best speed up for months on Polaris 20, at least.
Coming from vacation with injured right ankle joint, so I haven't had
time for testing before commit. But 'glmark2' numbers are better than
before all the Spectre shit (~8-9%?!).
In German: 'Da geht noch was...' ;-)
Greeting
Bas Nieuwenhuizen writes:
> Reviewed-by: Bas Nieuwenhuizen
Thanks to you, Jason and Lionel for reviewing the code and helping
improve it.
--
-keith
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