Re: [Mesa-dev] [PATCH] radv: optimize vkCmd{Set, Reset}Event() a little bit

FWIW none of our released Vulkan games will be using these functions. On 29 June 2018 at 03:28, Dieter Nützel wrote: > Tested-by: Dieter Nützel > > on RX 580 with F1 2017. > > Dieter > > > Am 28.06.2018 12:21, schrieb Samuel Pitoiset: > >> Always emitting a bottom-of-pipe event is quite dumb. I

Re: [Mesa-dev] [PATCH] radv: optimize vkCmd{Set, Reset}Event() a little bit

On 06/29/2018 09:24 AM, Alex Smith wrote: FWIW none of our released Vulkan games will be using these functions. We should be able to optimize CmdPipelineBarrier() too, but that's a bit more complicated. On 29 June 2018 at 03:28, Dieter Nützel > wrote: T

[Mesa-dev] [PATCH] gallium/u_vbuf: drop min/max-scanning for empty indirect draws

When building with asserts enabled, we'll end up triggering an assert in pipe_buffer_map_range down this code-path, due to trying to map an empty range. Even if we avoid that, we'll trigger another assert a bit later, because u_vbuf_get_minmax_index returns a min-index of -1 here, which gets promot

[Mesa-dev] [PATCH 1/4] anv/cmd_buffer: never shrink the push constant buffer size

If we have to re-emit push constant data, we need to re-emit all of it. --- src/intel/vulkan/anv_cmd_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index 33687920a38..3e9f000f7b8 100644 --- a/src

[Mesa-dev] [PATCH 4/4] anv/cmd_buffer: only emit state base address if the address changes

--- src/intel/vulkan/anv_private.h | 5 + src/intel/vulkan/genX_cmd_buffer.c | 12 +++- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 510471da602..1a9ab7013f2 100644 --- a/src/intel/vulkan/anv_

[Mesa-dev] [PATCH 3/4] anv/cmd_buffer: make descriptors dirty when emitting base state address

Every time we emit a new state base address we will need to re-emit our binding tables, since they might have been emitted with a different base state adress. --- src/intel/vulkan/genX_cmd_buffer.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/i

[Mesa-dev] [PATCH 2/4] anv/cmd_buffer: clean dirty push constants flag after emitting push constants

--- src/intel/vulkan/genX_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 97b321ccaeb..66d1ef7d786 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3008,6 +

Re: [Mesa-dev] [PATCH v3] virgl: Add support for glGetMultisample

On Thu, Jun 28, 2018 at 7:49 PM Gert Wollny wrote: > > Am Donnerstag, den 28.06.2018, 18:09 +0200 schrieb Erik Faye-Lund: > > It still seems kinda strange (and fragile) to me to try to enumerate > > all possible sample locations up-front instead of querying a given > > texture for it's sample-loca

Re: [Mesa-dev] [PATCH 1/2] mesa: MESA_framebuffer_flip_y extension [v2]

On Thu, Jun 28, 2018 at 11:12 PM Fritz Koenig wrote: > > Adds an extension to glFramebufferParameteri > that will specify if the framebuffer is vertically > flipped. Historically system framebuffers are > vertically flipped and user framebuffers are not. > Checking to see the state was done by loo

[Mesa-dev] [PATCH v2 12/18] mesa: add ARB_draw_indirect support to compat profile

v2: add missing ARB_base_instance support --- src/mesa/main/bufferobj.c| 3 +- src/mesa/main/extensions_table.h | 2 +- src/mesa/vbo/vbo_exec_array.c| 71 +++- 3 files changed, 72 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/bufferobj.c b/src/

[Mesa-dev] [PATCH v2 14/18] mesa: add compat profile support for ARB_multi_draw_indirect

v2: add missing ARB_base_instance support --- src/mesa/main/extensions_table.h | 2 +- src/mesa/vbo/vbo_exec_array.c| 77 +++- 2 files changed, 76 insertions(+), 3 deletions(-) diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h index

[Mesa-dev] [PATCH v4] virgl: Add support for glGetMultisample

Use caps to obtain the multisample sample positions for up to 16 positions and implement the according Gallium interface. This implemenation (plus its counterpart in virglrenderer) assume that the fixed sample position are always the same for a given number of samples over the whole live time of a

Re: [Mesa-dev] [PATCH v4] virgl: Add support for glGetMultisample

On Fri, Jun 29, 2018 at 12:39 PM Gert Wollny wrote: > > Use caps to obtain the multisample sample positions for up to 16 > positions and implement the according Gallium interface. > > This implemenation (plus its counterpart in virglrenderer) assume that > the fixed sample position are always the

Re: [Mesa-dev] [PATCH v4] virgl: Add support for glGetMultisample

On Fri, Jun 29, 2018 at 12:52 PM Erik Faye-Lund wrote: > > On Fri, Jun 29, 2018 at 12:39 PM Gert Wollny > wrote: > > > > Use caps to obtain the multisample sample positions for up to 16 > > positions and implement the according Gallium interface. > > > > This implemenation (plus its counterpart

[Mesa-dev] [PATCH 0/3] nv50/ir: Cleanups to Target*::initOpInfo()

I don't have push access. Rhys Perry (3): nv50/ir: improve maintainability of Target*::initOpInfo() configure: require c++11 for the gallium nouveau driver nv50/ir: use range-based for loops in Target*::initOpInfo() configure.ac | 4 ++ .../nouveau/co

[Mesa-dev] [PATCH 3/3] nv50/ir: use range-based for loops in Target*::initOpInfo()

Signed-off-by: Rhys Perry --- .../nouveau/codegen/nv50_ir_target_nv50.cpp| 54 +++--- .../nouveau/codegen/nv50_ir_target_nvc0.cpp| 16 +++ 2 files changed, 34 insertions(+), 36 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.c

[Mesa-dev] [PATCH 1/3] nv50/ir: improve maintainability of Target*::initOpInfo()

This is mainly useful for when one needs to add new opcodes in a painless and reliable way. Signed-off-by: Rhys Perry Reviewed-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 21 - .../drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp | 20 ++

[Mesa-dev] [PATCH 2/3] configure: require c++11 for the gallium nouveau driver

Signed-off-by: Rhys Perry --- configure.ac | 4 1 file changed, 4 insertions(+) diff --git a/configure.ac b/configure.ac index f135d05736..16d1832578 100644 --- a/configure.ac +++ b/configure.ac @@ -2678,6 +2678,10 @@ if test -n "$with_gallium_drivers"; then HAVE_GALLIUM_NOUVEA

Re: [Mesa-dev] [PATCH 0/3] nv50/ir: Cleanups to Target*::initOpInfo()

Just read the IRC logs and saw that things seemed to settle to "let's not require c++11 in nouveau", so ignore the second and third patches I guess. On Fri, Jun 29, 2018 at 11:57 AM, Rhys Perry wrote: > I don't have push access. > > Rhys Perry (3): > nv50/ir: improve maintainability of Target*:

Re: [Mesa-dev] [PATCH 2/3] meson: do not use the deprecated wayland-scanner "code"

On Thursday, 2018-06-28 15:35:45 +0100, Emil Velikov wrote: > From: Emil Velikov > > With version v1.15 the "code" option was deprecated in favour of > "private-code" or "public-code". > > Before the interface symbol generated was exported (which is a bad idea > since it's internal implementatio

Re: [Mesa-dev] [PATCH] glsl: enable EXT_texture_array by default in 1.30

NAK. The extension was not made core in GL 3.0. Many of the features were integrated into GL 3.0, but the actual extension text was not merged. (As is often true with extensions' functionality being integrated into core specs.) These enables control various functions like texture2DArray() and so o

Re: [Mesa-dev] [PATCH 1/3] nv50/ir: improve maintainability of Target*::initOpInfo()

On Fri, Jun 29, 2018 at 6:57 AM, Rhys Perry wrote: > This is mainly useful for when one needs to add new opcodes in a painless > and reliable way. > > Signed-off-by: Rhys Perry > Reviewed-by: Karol Herbst > --- > .../drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 21 > -

Re: [Mesa-dev] [PATCH] src/egl/Makefile: fix build race

On Thursday, 2018-06-28 23:01:59 +0100, Ross Burton wrote: > There is a parallel make build issue in src/egl/drivers/dri2/ > for wayland builds. Can be reproduced with: > > $ rm src/egl/drivers/dri2/*.h src/egl/drivers/dri2/platform_wayland.lo > $ make -C src/egl/ drivers/dri2/platform_wayland.lo

Re: [Mesa-dev] [PATCH] glsl: enable EXT_texture_array by default in 1.30

On 29/06/18 21:34, Ilia Mirkin wrote: NAK. The extension was not made core in GL 3.0. Many of the features were integrated into GL 3.0, but the actual extension text was not merged. (As is often true with extensions' functionality being integrated into core specs.) These enables control various

Re: [Mesa-dev] [PATCH] glsl: enable EXT_texture_array by default in 1.30

On Fri, Jun 29, 2018 at 8:31 AM, Timothy Arceri wrote: > On 29/06/18 21:34, Ilia Mirkin wrote: >> >> NAK. >> >> The extension was not made core in GL 3.0. Many of the features were >> integrated into GL 3.0, but the actual extension text was not merged. >> (As is often true with extensions' functi

Re: [Mesa-dev] [PATCH] radv: optimize vkCmd{Set, Reset}Event() a little bit

Ohhh! ;-) My son and I were so excited, that we can play all (?) of your GREAT titels (DiRT Rally/F1 2017) with FF under 4.17+ with our wireless Gasia Co.,Lt PS(R) Gamepad compatible hardware, now. We have to switch it from PS(R) Gamepad mode to XBOX 360 For Windows mode before game/Steam s

[Mesa-dev] [PATCH v2] nv50/ir: improve maintainability of Target*::initOpInfo()

This is mainly useful for when one needs to add new opcodes in a painless and reliable way. Signed-off-by: Rhys Perry --- Changes in v2: - use operation instead of uint32_t - use ARRAY_SIZE() - add "set below" comments I don't have push access. .../nouveau/codegen/nv50_ir_target_nv50.cpp

[Mesa-dev] [PATCH 00/18] ARB_gl_spirv series 3: support for atomic counters

Hi, this is the third series for the ongoing support for ARB_gl_spirv. The main focus of this series is providing support for atomic counters. More than half of the patches are for spirv/nir, as atomic counters is a feature not included on Vulkan. Note that the need of supporting atomic counters

[Mesa-dev] [PATCH 03/19] nir/linker: use empty block info to assign uniform locations

For the cases of uniforms that doesn't have an explicit location. Under ARB_gl_spirv those are exceptions, like uniform atomic counters. --- src/compiler/glsl/gl_nir_link_uniforms.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/compiler/g

[Mesa-dev] [PATCH 09/18] nir/spirv: Fix atomic counter (multidimensional-)arrays

From: Antia Puentes When constructing NIR if we have a SPIR-V uint variable and the storage class is SpvStorageClassAtomicCounter, we store as NIR's glsl_type an atomic_uint to reflect the fact that the variable is an atomic counter. However, we were tweaking the type only for atomic_uint scalar

[Mesa-dev] [PATCH 08/18] compiler: utility to get the depth of multidimensional array

From: Antia Puentes --- src/compiler/glsl_types.h | 15 +++ src/compiler/nir_types.cpp | 6 ++ src/compiler/nir_types.h | 3 +++ 3 files changed, 24 insertions(+) diff --git a/src/compiler/glsl_types.h b/src/compiler/glsl_types.h index efc63248656..e5dcd39180e 100644 --- a/

[Mesa-dev] [PATCH 13/18] nir/types: Add wrappers for a couple of atomic counter methods

From: Neil Roberts --- src/compiler/nir_types.cpp | 12 src/compiler/nir_types.h | 3 +++ 2 files changed, 15 insertions(+) diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp index a3c39d11383..526ecc1aa5a 100644 --- a/src/compiler/nir_types.cpp +++ b/src/compi

[Mesa-dev] [PATCH 04/18] spirv/nir: SpvStorageClassAtomicCounter support on vtn_storage_class_to_mode

Atomic Counters are uniforms per spec. --- src/compiler/spirv/vtn_variables.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index 574f422ceab..6a2144ceabb 100644 --- a/src/compiler/spirv/vtn_variable

[Mesa-dev] [PATCH 05/18] spirv/nir: add offset at vtn_variable

Also initialize it on var_decoration_cb This is equivalent to nir_variable.offset, used to store the location an atomic counter is stored at. --- src/compiler/spirv/vtn_private.h | 1 + src/compiler/spirv/vtn_variables.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/src/compiler/spirv

[Mesa-dev] [PATCH 12/18] spirv/nir: add capability check for SpvCapabilityAtomicStorage

Capability that informs if atomic counters are supported. From SPIR-V 1.0 spec, section 3.7, "Storage Class", item 10 from table: (Column "Storage Class"): "AtomicCounter For holding atomic counters. Visible across all functions of the current invocation. Atomic counter-specific memory

[Mesa-dev] [PATCH 06/18] nir_types: add glsl_atomic_uint_type() helper

--- src/compiler/nir_types.cpp | 6 ++ src/compiler/nir_types.h | 1 + 2 files changed, 7 insertions(+) diff --git a/src/compiler/nir_types.cpp b/src/compiler/nir_types.cpp index d2b2a93b207..1fc6bfa7175 100644 --- a/src/compiler/nir_types.cpp +++ b/src/compiler/nir_types.cpp @@ -477,3 +477

[Mesa-dev] [PATCH 11/18] spirv/nir: add atomic counter support on vtn_handle_ssbo_or_shared_atomic

So renamed to a more general vtn_handle_atomics --- src/compiler/spirv/spirv_to_nir.c | 90 --- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index c31293a77be..270f263d047 1

[Mesa-dev] [PATCH 14/18] nir/linker: Add a pure NIR implementation of the atomic counter linker

From: Neil Roberts This is mostly just a straight-forward conversion of link_assign_atomic_counter_resources to C directly using nir variables instead of GLSL IR variables. It is based on the version of link_assign_atomic_counter_resources in 6b8909f2d1906. I’m noting this here to make it easier

[Mesa-dev] [PATCH 02/18] compiler/glsl: refactor empty_uniform_block utilities to linker_util

This includes: * Move the defition of empty_uniform_block to linker_util.h * Move find_empty_block (with a rename) to linker_util.h * Refactor some code at linker.cpp to a new method at linker_util.h (link_util_update_empty_uniform_locations) So all that code could be used by the GLSL li

[Mesa-dev] [PATCH 17/18] i965: enable AtomicStorage capability for gen7+

That is the same gen requirement for ARB_shader_atomic_counters. --- src/mesa/drivers/dri/i965/brw_context.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 9ced230ec14..e755de6241a 100644 --- a/src/mesa/d

[Mesa-dev] [PATCH 16/18] mesa/glspirv: lower workgroup access to offsets

From: Antia Puentes This will perform the CS shared lowering. See 8761a04d0d93 --- src/mesa/main/glspirv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/main/glspirv.c b/src/mesa/main/glspirv.c index c585bc51bbf..8ad6c373914 100644 --- a/src/mesa/main/glspirv.c +++ b/src/mesa/main

[Mesa-dev] [PATCH 15/18] nir: Fix OpAtomicCounterIDecrement for uniform atomic counters

From: Antia Puentes From the SPIR-V specification, OpAtomicIDecrement: "The instruction's result is the Original Value." However, we were implementing it, for uniform atomic counters, as a pre-decrement operation. Renamed the former nir intrinsic 'atomic_counter_dec*' to 'atomic_counter_pre_dec

[Mesa-dev] [PATCH 10/18] spirv/nir: initialize offset on the nir var at vtn_create_variable

This is convenient when dealing with atomic counter uniforms. The alternative would be doing that at vtn_handle_atomics. --- src/compiler/spirv/vtn_variables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c index c75492e

[Mesa-dev] [PATCH 18/18] i965: Use the new nir atomic counter linker for SPIR-V shaders

From: Neil Roberts --- src/mesa/drivers/dri/i965/brw_link.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index 8bc97fa4f3e..1071056f149 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/d

[Mesa-dev] [PATCH 07/18] spirv/nir: tweak nir type when storage class is SpvStorageClassAtomicCounter

GLSL types differentiates uint from atomic uint. On SPIR-V the type is uint, and the variable has a specific storage class. So we need to tweak the type based on the storage class. Ideally we would like to get the proper type at vtn_handle_type, but we don't have the storage class at that moment.

[Mesa-dev] [PATCH 03/18] nir/linker: use empty block info to assign uniform locations

For the cases of uniforms that doesn't have an explicit location. Under ARB_gl_spirv those are exceptions, like uniform atomic counters. --- src/compiler/glsl/gl_nir_link_uniforms.c | 31 +-- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/compiler/g

[Mesa-dev] [PATCH 01/18] nir/linker: handle uniforms without explicit location

ARB_gl_spirv points that uniforms in general need explicit location. But there are still some cases of uniforms without location, like for example uniform atomic counters. Those doesn't have a location from the OpenGL point of view (they are identified with a binding), but Mesa internally assigns i

Re: [Mesa-dev] [PATCH v2] nv50/ir: improve maintainability of Target*::initOpInfo()

Reviewed-by: Ilia Mirkin On Fri, Jun 29, 2018 at 9:51 AM, Rhys Perry wrote: > This is mainly useful for when one needs to add new opcodes in a painless > and reliable way. > > Signed-off-by: Rhys Perry > --- > Changes in v2: > - use operation instead of uint32_t > - use ARRAY_SIZE() > - add "se

[Mesa-dev] [PATCH v2 0/2] r600: Fix array texture slice index evaluation

I reworded parts of the comments, and simplified the patch against the shader to correct the piglit failures and taking into account that a shader can not set an offset for the array index at all. Apart from the dEQP tests I've run ./piglit run gpu -t texture with no changes. (I always got hang

[Mesa-dev] [PATCH v2 1/2] r600: correct texture offset for array index lookup

For texture array lookup the slice index is evaluated according to idx = floor(z + 0.5) This patch implements the first part by adding 0.5 to the according texture coordinate when appropriate. Fixes multi-sample tests out of: dEQP-GLES3.functional.texture.shadow.2d_array.* dEQP-GLES3.functi

[Mesa-dev] [PATCH v2 2/2] r600: set rounding mode for texture array layer selection

The evaluation of the array layer index is "floor(z+0.5)", and the default rounding mode doesn't correctly evaluate this. Therefore, set the rounding mode to "trunc" and z-filter mode to "point". For other textures make sure the the default rounding mode and z-filter are used. Fixes single-sample

Re: [Mesa-dev] [PATCH 32/53] intel/fs: Mark LINTERP opcode as writing accumulator implicitly on pre-Gen7.

Quoting Jason Ekstrand (2018-05-24 14:56:14) > From: Francisco Jerez > > --- > src/intel/compiler/brw_shader.cpp | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/src/intel/compiler/brw_shader.cpp > b/src/intel/compiler/brw_shader.cpp > index 141b64e..61211ef 100644 >

Re: [Mesa-dev] [PATCH 08/11] radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2

Quoting Marek Olšák (2018-06-18 16:33:09) > From: Marek Olšák > > Cc: 18.1 > --- > src/gallium/drivers/radeonsi/si_blit.c | 30 +++--- > 1 file changed, 27 insertions(+), 3 deletions(-) > > diff --git a/src/gallium/drivers/radeonsi/si_blit.c > b/src/gallium/drivers/radeons

Re: [Mesa-dev] [PATCH v2 1/2] r600: correct texture offset for array index lookup

Am 29.06.2018 um 16:35 schrieb Gert Wollny: > For texture array lookup the slice index is evaluated according to > idx = floor(z + 0.5) > > This patch implements the first part by adding 0.5 to the according > texture coordinate when appropriate. > > Fixes multi-sample tests out of: > dEQP-GL

Re: [Mesa-dev] [PATCH v2 2/2] r600: set rounding mode for texture array layer selection

Am 29.06.2018 um 16:35 schrieb Gert Wollny: > The evaluation of the array layer index is "floor(z+0.5)", and the default > rounding mode doesn't correctly evaluate this. Therefore, set the rounding > mode to "trunc" and z-filter mode to "point". > For other textures make sure the the default roundi

Re: [Mesa-dev] [PATCH 1/2] mesa: MESA_framebuffer_flip_y extension [v2]

On Fri, Jun 29, 2018 at 1:50 AM Erik Faye-Lund wrote: > > On Thu, Jun 28, 2018 at 11:12 PM Fritz Koenig wrote: > > > > Adds an extension to glFramebufferParameteri > > that will specify if the framebuffer is vertically > > flipped. Historically system framebuffers are > > vertically flipped and u

Re: [Mesa-dev] [PATCH 08/11] radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2

On Fri, Jun 29, 2018 at 11:40 AM, Dylan Baker wrote: > Quoting Marek Olšák (2018-06-18 16:33:09) >> From: Marek Olšák >> >> Cc: 18.1 >> --- >> src/gallium/drivers/radeonsi/si_blit.c | 30 +++--- >> 1 file changed, 27 insertions(+), 3 deletions(-) >> >> diff --git a/src/galli

Re: [Mesa-dev] [PATCH 08/11] radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2

Quoting Marek Olšák (2018-06-29 09:48:08) > On Fri, Jun 29, 2018 at 11:40 AM, Dylan Baker wrote: > > Quoting Marek Olšák (2018-06-18 16:33:09) > >> From: Marek Olšák > >> > >> Cc: 18.1 > >> --- > >> src/gallium/drivers/radeonsi/si_blit.c | 30 +++--- > >> 1 file changed, 27

[Mesa-dev] [PATCH 1/2] mesa: MESA_framebuffer_flip_y extension [v3]

Adds an extension to glFramebufferParameteri that will specify if the framebuffer is vertically flipped. Historically system framebuffers are vertically flipped and user framebuffers are not. Checking to see the state was done by looking at the name field. This adds an explicit field. v2: * updat

[Mesa-dev] [ANNOUNCE] mesa 18.1.3

Hi List, Mesa 18.1.3 is now available. This is a bug fix point release in the 18.1 series. In this release we have: - numerous fixes for radv - some fixes for common radeon code - several meson fixes - fixes for autotools with non-gnu grep - fixes for both the nir and glsl compilers - An i9

[Mesa-dev] [PATCH] i965: fix typo (wrong gen number) in comment

--- src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index b279f01e1a1..921b420ab81 100644 --- a/src/mesa/drivers/dri/i965/genX_state_uplo

Re: [Mesa-dev] [PATCH v2 12/18] mesa: add ARB_draw_indirect support to compat profile

Reviewed-by: Marek Olšák Marek On Fri, Jun 29, 2018 at 5:22 AM, Timothy Arceri wrote: > v2: add missing ARB_base_instance support > --- > src/mesa/main/bufferobj.c| 3 +- > src/mesa/main/extensions_table.h | 2 +- > src/mesa/vbo/vbo_exec_array.c| 71 ++

Re: [Mesa-dev] [PATCH v2 14/18] mesa: add compat profile support for ARB_multi_draw_indirect

Reviewed-by: Marek Olšák Marek On Fri, Jun 29, 2018 at 5:23 AM, Timothy Arceri wrote: > v2: add missing ARB_base_instance support > --- > src/mesa/main/extensions_table.h | 2 +- > src/mesa/vbo/vbo_exec_array.c| 77 +++- > 2 files changed, 76 insertions(+), 3 d

Re: [Mesa-dev] [PATCH] gallium/u_vbuf: drop min/max-scanning for empty indirect draws

Reviewed-by: Marek Olšák Marek On Thu, Jun 28, 2018 at 9:22 AM, Erik Faye-Lund wrote: > When building with asserts enabled, we'll end up triggering an assert > in pipe_buffer_map_range down this code-path, due to trying to map > an empty range. Even if we avoid that, we'll trigger another asser

[Mesa-dev] [PATCH 0/6] anv,nir: Move large constants to a UBO

This little series adds an optimization pass to NIR and wires up up in anv that moves large constant variables to a UBO. This fixes a farily common case in some filter or ambient occlusion shaders where they put some sort of look-up table in the shader itself. This series takes Skyrim Special Edi

[Mesa-dev] [PATCH 2/6] nir: Add a concept of constant data associated with a shader

This commit adds a concept to NIR of having a blob of constant data associated with a shader. Instead of being a UBO or uniform that can be manipulated by the client, this constant data considered part of the shader and remains constant across all invocations of the given shader until the end of t

[Mesa-dev] [PATCH 6/6] anv, intel: Enable nir_opt_large_constants for Vulkan

According to RenderDoc, this shaves 99.6% of the run time off of the ambient occlusion pass in Skyrim Special Edition when running under DXVK and shaves 92% off the runtime for a reasonably representative frame. When running the actual game, Skyrim goes from being a slide-show to a very stable and

[Mesa-dev] [PATCH 5/6] anv: Add state setup support for shader constants

--- .../vulkan/anv_nir_apply_pipeline_layout.c| 47 src/intel/vulkan/anv_private.h| 1 + src/intel/vulkan/genX_cmd_buffer.c| 72 ++- 3 files changed, 101 insertions(+), 19 deletions(-) diff --git a/src/intel/vulkan/anv_nir_apply_pipeli

[Mesa-dev] [PATCH 3/6] nir: Add a large constants optimization pass

This pass searches for reasonably large local variables which can be statically proven to be constant and moves them into shader constant data. This is especially useful when large tables are baked into the shader source code because they can be moved into a UBO by the driver to reduce register pr

[Mesa-dev] [PATCH 4/6] anv: Add support for shader constant data to the pipeline cache

--- src/intel/vulkan/anv_blorp.c | 1 + src/intel/vulkan/anv_pipeline.c | 12 src/intel/vulkan/anv_pipeline_cache.c | 26 ++ src/intel/vulkan/anv_private.h| 6 ++ 4 files changed, 45 insertions(+) diff --git a/src/intel/vulkan/anv_

[Mesa-dev] [PATCH 1/6] nir: Add a deref_instr_has_indirect helper

--- src/compiler/nir/nir.h | 2 ++ src/compiler/nir/nir_deref.c | 18 ++ 2 files changed, 20 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index c16ce547642..e35bef612df 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -987,6

Re: [Mesa-dev] [PATCH] i965: fix typo (wrong gen number) in comment

On Friday, June 29, 2018 11:39:34 AM PDT Caio Marcelo de Oliveira Filho wrote: > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c > b/src/mesa/drivers/dri/i965/genX_state_upl

Re: [Mesa-dev] [PATCH v2 2/3] st/mesa: Fall back to R8G8B8A8_SRGB for ETC2

On Fri, Jun 22, 2018 at 9:59 AM, Tomeu Vizoso wrote: > If the driver doesn't support PIPE_FORMAT_B8G8R8A8_SRGB, fall back to > PIPE_FORMAT_R8G8B8A8_SRGB. > > Drivers such as Virgl will have a hard time supporting > PIPE_FORMAT_B8G8R8A8_SRGB when the host runs GLES, as GL_ABGR isn't as > well supor

Re: [Mesa-dev] [PATCH v2 3/3] st/mesa: Also check for PIPE_FORMAT_A8R8G8B8_SRGB for texture_sRGB

For the series: Reviewed-by: Marek Olšák Marek On Fri, Jun 22, 2018 at 9:59 AM, Tomeu Vizoso wrote: > and PIPE_FORMAT_R8G8B8A8_SRGB, as well. > > The reason for this is that when Virgl runs with GLES on the host, it > cannot directly upload textures in BGRA. > > So to avoid a conversion step,

Re: [Mesa-dev] [PATCH v3 4/4] gallium/llvmpipe: Enable support bptc format.

For the series: Reviewed-by: Marek Olšák Marek On Tue, Jun 26, 2018 at 4:30 PM, Denis Pauk wrote: > v2: none > v3: none > > Signed-off-by: Denis Pauk > CC: Marek Olšák > CC: Rhys Perry > CC: Matt Turner > --- > src/gallium/drivers/llvmpipe/lp_screen.c | 3 +-- > src/gallium/drivers/l

Re: [Mesa-dev] [PATCH] radeonsi: Add debug option to enable LLVM GlobalISel

Hi Tom, We shouldn't use gallivm if possible and instead c++ helpers should be added into ac_llvm_helper.cpp with the ac prefix. With that done: Reviewed-by: Marek Olšák Thanks, Marek On Tue, Jun 26, 2018 at 11:00 PM, Tom Stellard wrote: > R600_DEBUG=gisel will tell LLVM to use GlobalISel rat

[Mesa-dev] [Bug 106842] Error de prueba

https://bugs.freedesktop.org/show_bug.cgi?id=106842 Andre Klapper changed: What|Removed |Added Component|Demos |Two QA Contact|mesa-dev@lists.f

Re: [Mesa-dev] [ANNOUNCE] mesa 18.1.3

On Fri, Jun 29, 2018 at 2:00 PM, Dylan Baker wrote: > Hi List, > > Mesa 18.1.3 is now available. This is a bug fix point release in the 18.1 > series. > > In this release we have: > - numerous fixes for radv > - some fixes for common radeon code > - several meson fixes > - fixes for autotools

Re: [Mesa-dev] [PATCH v2 1/2] r600: correct texture offset for array index lookup

Am Freitag, den 29.06.2018, 17:42 +0200 schrieb Roland Scheidegger: [...] Thanks for the review > > So for gather4_O (where you'd need to do it differently) it must not > be > done, but for gather4 it has to be done? > Still doesn't make all that much sense to me. The hw may be weird but > I don

[Mesa-dev] [Bug 77449] Tracker bug for all bugs related to Steam titles

https://bugs.freedesktop.org/show_bug.cgi?id=77449 Bug 77449 depends on bug 99813, which changed state. Bug 99813 Summary: F1 2015 rendering broken at medium quality https://bugs.freedesktop.org/show_bug.cgi?id=99813 What|Removed |Added -

Re: [Mesa-dev] [ANNOUNCE] mesa 18.1.3

Quoting Ilia Mirkin (2018-06-29 14:48:30) > On Fri, Jun 29, 2018 at 2:00 PM, Dylan Baker wrote: > > Hi List, > > > > Mesa 18.1.3 is now available. This is a bug fix point release in the 18.1 > > series. > > > > In this release we have: > > - numerous fixes for radv > > - some fixes for common ra

[Mesa-dev] [PATCH v8 01/33] nv50/ir/ra: Fix copying compound for moves

From: Connor Abbott In order to reduce moves when coalescing multiple registers into a larger register, RA will try to coalesce MERGE instructions with their definitions. For example, for something like this in GLSL: uint a = ...; uint b = ...; uint64 x = packUint2x32(a, b); The compiler will t

[Mesa-dev] [PATCH v8 06/33] nouveau: add env var to make nir default

v2: allow for non debug builds as well v3: move reading out env var more global disable tg4 with multiple offsets with nir disable caps for 64 bit types v6: nv50 support disable MS images disable bindless textures Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouvea

[Mesa-dev] [PATCH v8 02/33] nvc0: print the shader type when dumping headers

this makes debugging the shader header a little easier Acked-by: Pierre Moreau Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/

[Mesa-dev] [PATCH v8 07/33] nouveau: fix nir and TGSI shader cache collision

Signed-off-by: Karol Herbst --- src/gallium/drivers/nouveau/nouveau_screen.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c b/src/gallium/drivers/nouveau/nouveau_screen.c index 03c1c74160f..7acf2050f10 100644 --- a/src/galliu

[Mesa-dev] [PATCH v8 00/33] Nouveau NIR support

I think this is finally getting complete. There are a handful of piglit and CTS regressions, but those are caused by issues in common nir and gallium code. Some features remain disabled like bindless textures, because there is more ground work needed to be able to properly do it with nir. Changes

[Mesa-dev] [PATCH v8 03/33] nvir: move common converter code in base class

v2: remove TGSI related bits Signed-off-by: Karol Herbst Reviewed-by: Pierre Moreau --- src/gallium/drivers/nouveau/Makefile.sources | 2 + .../nouveau/codegen/nv50_ir_from_common.cpp | 107 ++ .../nouveau/codegen/nv50_ir_from_common.h | 58 ++ .../nouveau/code

[Mesa-dev] [PATCH v8 04/33] nvir: add lowering helper

this is mostly usefull for lazy IR converters not wanting to deal with 64 bit lowering and other illegal stuff v5: also handle SAT v6: rename type variables fixed lowering of NEG add lowering of NOT v8: don't require C++11 features Signed-off-by: Karol Herbst --- src/gallium/drivers/nou

[Mesa-dev] [PATCH v8 14/33] nvir/nir: implement nir_load_const_instr

v8: fix loading 8/16 bit constants Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 28 +++ 1 file changed, 28 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_n

[Mesa-dev] [PATCH v8 15/33] nvir/nir: add skeleton for nir_intrinsic_instr

Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp| 17 + 1 file changed, 17 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_nir.cpp index 3084f32abb4..a990acfc35

[Mesa-dev] [PATCH v8 16/33] nvir/nir: implement nir_alu_instr handling

v2: user bitfield_insert instead of bfi rework switch helper macros remove some lowering code (LoweringHelper is now used for this) v3: add pack_half_2x16_split add unpack_half_2x16_split_x/y v5: replace first argument with nullptr in loadImm calls prefer getSSA over getScratch v8:

[Mesa-dev] [PATCH v8 08/33] nvir/nir: run some passes to make the conversion easier

v2: add constant_folding v6: print non final NIR only for verbose debugging v8: add passes we will need for OpenCL compute shaders Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 41 +++ 1 file changed, 41 insertions(+) diff --git a/src/gallium/dr

[Mesa-dev] [PATCH v8 05/33] nouveau: add support for nir

not all those nir options are actually required, it just made the work a little easier. v2: fix asserts parse compute shaders don't lower bitfield_insert v3: fix memory leak v4: don't lower fmod32 v5: set lower_all_io_to_temps to false fix memory leak because we take over ownership of

[Mesa-dev] [PATCH v8 09/33] nvir/nir: track defs and provide easy access functions

v2: add helper function for indirects v4: add new getIndirect overload for easier use v5: use getSSA for ssa values we can just create the values for unassigned registers in getSrc v6: always create at least 32 bit values v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../n

[Mesa-dev] [PATCH v8 27/33] nvir/nir: implement geometry shader nir_intrinsics

v4: use smarter getIndirect helper use new getSlotAddress helper use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 27 +++ 1 file changed, 27 insertions(+) diff --git a/src/gallium/drivers

[Mesa-dev] [PATCH v8 32/33] nvir/nir: implement load_per_vertex_output

v4: use smarter getIndirect helper use new getSlotAddress helper v5: use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 23 +++ 1 file changed, 23 insertions(+) diff --git a/src/gallium/drivers

[Mesa-dev] [PATCH v8 13/33] nvir/nir: parse NIR shader info

v2: parse a few more fields v3: add special handling for GL_ISOLINES v8: set info->prop.fp.readsSampleLocations don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 325 +- 1 file changed, 323 insertions(+), 2 deletions(

[Mesa-dev] [PATCH v8 17/33] nvir/nir: implement nir_intrinsic_load_uniform

v2: use new getIndirect helper fixes symbols for 64 bit types v4: use smarter getIndirect helper simplify address calculation use loadFrom helper v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../drivers/nouveau/codegen/nv50_ir_from_nir.cpp | 10 ++ 1

[Mesa-dev] [PATCH v8 10/33] nvir/nir: add nir type helper functions

v4: treat imul as unsigned v5: remove pointless !! v7: inot is unsigned as well v8: don't require C++11 features Signed-off-by: Karol Herbst --- .../nouveau/codegen/nv50_ir_from_nir.cpp | 115 ++ 1 file changed, 115 insertions(+) diff --git a/src/gallium/drivers/nouveau/cod

[Mesa-dev] [PATCH v8 19/33] nvir/nir: implement load_(interpolated_)input/output

v3: and load_output v4: use smarter getIndirect helper use new getSlotAddress helper v5: don't use const_offset directly fix for indirects v6: add support for interpolateAt v7: fix compiler warnings add load_barycentric_sample handle load_output for fragment shaders v8: set info->pr

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