[Mesa-dev] [AppVeyor] mesa master #6239 failed

Build mesa 6239 failed Commit f1873956db by Iago Toral Quiroga on 11/21/2017 10:33 AM: i965/vec4: fix splitting of interleaved attributes\n\nWhen we split an instruction that reads an uniform value\n(vstride 0) we need to respect the vstride on the second\nhalf

Re: [Mesa-dev] [PATCH] Adding tiled to linear conversion functionality

On 11/23/2017 9:40 PM, Ilia Mirkin wrote: On Wed, Nov 22, 2017 at 6:00 AM, Satyajit Sahu wrote: Add tiled to linear conversion and expose outside mesa. Also exposing the create compute and destroy surface fucntions outside. typo: functions Done Change-Id: Ie464ba0eac5d80048797bef1f6ad730

Re: [Mesa-dev] 10-bit Mesa/Gallium support

On 2017-11-23 07:31 PM, Mario Kleiner wrote:> > 3. In principle the clean solution for nouveau would be to upgrade the> ddx to drmAddFB2 ioctl, and use xbgr2101010 scanout to support> everything back to nv50+, but everything we have in X or Wayland is> meant for xrgb2101010 not xbgr2101010. And we

Re: [Mesa-dev] 10-bit Mesa/Gallium support

Apologies for the badly formatted followup before, let's try that again: On 2017-11-23 07:31 PM, Mario Kleiner wrote: > > 3. In principle the clean solution for nouveau would be to upgrade the > ddx to drmAddFB2 ioctl, and use xbgr2101010 scanout to support > everything back to nv50+, but everyt

Re: [Mesa-dev] [PATCH 2/3] util: Add a SHA1 unit test program

On Thursday, 2017-11-23 11:08:05 -0800, Matt Turner wrote: > --- > src/util/Makefile.am | 3 ++- > src/util/mesa-sha1_test.c | 65 > +++ > 2 files changed, 67 insertions(+), 1 deletion(-) > create mode 100644 src/util/mesa-sha1_test.c > > diff -

Re: [Mesa-dev] Mesa 17.2.6 release candidate

On Thu, 2017-11-23 at 15:49 -0800, Matt Turner wrote: > I would like to include the three patch series I sent today in 17.2.6. > It fixes our SHA1 implementation on big endian, adds a test, and fixes > another test. > > I hope it'll be reviewed and in master before the planned 17.2.6 release. OK.

[Mesa-dev] [AppVeyor] mesa master #6240 completed

Build mesa 6240 completed Commit dc391a406a by Samuel Pitoiset on 11/22/2017 7:13 PM: radv/winsys: improve error messages when the buffer list creation failed\n\nSigned-off-by: Samuel Pitoiset \nReviewed-by: Dave Airlie \nReviewed-by: Bas Nieuwenhuizen

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Thursday, 2017-11-23 11:08:04 -0800, Matt Turner wrote: > The code defines a macro blk0(i) based on the preprocessor condition > BYTE_ORDER == LITTLE_ENDIAN. If true, blk0(i) is defined as a byte swap > operation. Unfortunately, if the preprocessor macros used in the test > are no defined, then

Re: [Mesa-dev] [PATCH] gl_table.py: add extern C guard for the generated glapitable.h

On Thursday, 2017-11-23 19:01:22 +, Emil Velikov wrote: > From: Emil Velikov > > Cc: mesa-sta...@lists.freedesktop.org > Cc: Dylan Baker > Signed-off-by: Emil Velikov Reviewed-by: Eric Engestrom > --- > src/mapi/glapi/gen/gl_table.py | 8 > 1 file changed, 8 insertions(+) > >

Re: [Mesa-dev] [PATCH 2/3] util: Add a SHA1 unit test program

On Friday, 2017-11-24 10:08:55 +, Eric Engestrom wrote: > On Thursday, 2017-11-23 11:08:05 -0800, Matt Turner wrote: > > --- > > src/util/Makefile.am | 3 ++- > > src/util/mesa-sha1_test.c | 65 > > +++ > > 2 files changed, 67 insertions(+), 1

[Mesa-dev] [PATCH mesa] st/dri: replace hard-coded array size with ARRAY_SIZE()

Signed-off-by: Eric Engestrom --- Could've sworn I had already seen someone post this patch; guess either I was mistaken, or it got lost on the way. --- src/gallium/state_trackers/dri/dri_screen.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/dri/d

Re: [Mesa-dev] [PATCH mesa 0/7] remove upstreamed specs

On Thursday, 2017-11-23 16:32:06 +, Emil Velikov wrote: > On 23 November 2017 at 16:04, Eric Engestrom > wrote: > > On Thursday, 2017-11-23 13:32:47 +, Emil Velikov wrote: > >> Hi Eric, > >> > >> On 22 November 2017 at 17:59, Eric Engestrom > >> wrote: > >> > A recent thread [1] made me

[Mesa-dev] [PATCH 01/51] nir: Prepare constant folding for 16-bits

Signed-off-by: Topi Pohjolainen --- src/compiler/nir/nir_opt_constant_folding.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index d6be807b3d..b63660ea4d 100644 --- a/src/compiler/nir/nir_opt_const

[Mesa-dev] [PATCH 04/51] glsl: Print 16-bit constants

--- src/compiler/glsl/ir_print_visitor.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/glsl/ir_print_visitor.cpp b/src/compiler/glsl/ir_print_visitor.cpp index ea14cdeb6c..ab9a35d73f 100644 --- a/src/compiler/glsl/ir_print_visitor.cpp +++ b/src/compiler/glsl/ir_print_visitor.

[Mesa-dev] [PATCH 02/51] nir: Prepare constant lowering for 16-bits constants

Signed-off-by: Topi Pohjolainen --- src/compiler/nir/nir_lower_load_const_to_scalar.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_load_const_to_scalar.c b/src/compiler/nir/nir_lower_load_const_to_scalar.c index e494facfd2..76eb1d3a12 100644

[Mesa-dev] [PATCH 08/51] glsl: Add more conversion ops to/from 16-bit floats

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/glsl_to_nir.cpp| 6 ++ src/compiler/glsl/ir_expression_operation.py | 16 ++-- src/compiler/glsl/ir_validate.cpp| 24 src/mesa/program/ir_to_mesa.cpp | 6 ++ s

[Mesa-dev] [PATCH 06/51] glsl: Add support for 16-bit float constants in nir-conversion

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/glsl_to_nir.cpp | 9 + 1 file changed, 9 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 1e636225c1..289f8be031 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/

[Mesa-dev] [PATCH 03/51] nir: Add 16-bit float support into algebraic opts

Signed-off-by: Topi Pohjolainen --- src/compiler/nir/nir_search.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c index dec56fee74..3b28da4a3f 100644 --- a/src/compiler/nir/nir_search.c +++ b/src/compiler/nir/nir_search.c @@ -2

[Mesa-dev] [PATCH 07/51] glsl: Add conversion ops to/from 16-bit floats

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/glsl_to_nir.cpp| 2 ++ src/compiler/glsl/ir.cpp | 8 src/compiler/glsl/ir_expression_operation.py | 5 + src/compiler/glsl/ir_validate.cpp| 8 src/mesa/program/ir_to_mesa.cpp

[Mesa-dev] i965: Kicking off fp16 glsl support

After Igalia's work on SPIRV 16-bit storage question arose how much is needed on top in order to optimize GLES lowp/mediump with 16-bit floats. I took glb 2.7 trex as a target and started drafting a glsl lowering pass re-typing mediump floats into float16. In parallel, I added bit by bit equivalent

[Mesa-dev] [PATCH 05/51] nir: Print 16-bit constants

Signed-off-by: Topi Pohjolainen --- src/compiler/nir/nir_print.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index fcc8025346..9ed23a74bb 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -27,6

[Mesa-dev] [PATCH 10/51] glsl: Allow 16-bit math

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/ir_validate.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/ir_validate.cpp b/src/compiler/glsl/ir_validate.cpp index 735e862141..d246af866d 100644 --- a/src/compiler/glsl/ir_validate.cpp +++ b

[Mesa-dev] [PATCH 09/51] glsl: Allow 16-bit neg() and dot()

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/ir_validate.cpp | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/ir_validate.cpp b/src/compiler/glsl/ir_validate.cpp index a20f52e527..735e862141 100644 --- a/src/compiler/glsl/ir_validate.cpp +++

[Mesa-dev] [PATCH 19/51] intel/compiler/fs: Add helpers for 16-bit null regs

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_builder.h | 12 1 file changed, 12 insertions(+) diff --git a/src/intel/compiler/brw_fs_builder.h b/src/intel/compiler/brw_fs_builder.h index 87394bc17b..633086c64b 100644 --- a/src/intel/compiler/brw_fs_builder.h +++ b/

[Mesa-dev] [PATCH 16/51] intel/compiler: Move type_size_scalar() into brw_shader.cpp

Next path will add another variant and in order not to make brw_fs.cpp any bigger it already is, add both in brw_shader.cpp instead. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 48 --- src/intel/compiler/brw_shader.cpp | 48

[Mesa-dev] [PATCH 20/51] intel/compiler/fs: Use two SIMD8 instructions for 16-bit math

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 3c70231be8..5751bb0ad7 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/

[Mesa-dev] [PATCH 21/51] intel/compiler/fs: Use 16-bit null dest with 16-bit math

Even though this doesn't seem to alter anything else than dumping it is more consistent. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_generator.cpp | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/comp

[Mesa-dev] [PATCH 36/51] intel/compiler/fs: Prepare nir_emit_if() for 16-bit sources

Comparison operations using 16-bit sources produce 16-bit results (0x/0x) instead of (0xFFF/0x). Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 11 --- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir

[Mesa-dev] [PATCH 12/51] intel/compiler/disasm: Print 16-bit IMM values

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_disasm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index c752e15331..da2a5d78dd 100644 --- a/src/intel/compiler/brw_disasm.c +++ b/src/intel/com

[Mesa-dev] [PATCH 22/51] intel/compiler/fs: Use 16-bit null dest with 16-bit compare

Otherwise EU-emitter will deduce wrong execution size when examining source types and finding 32-bit wide register. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 16 +--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_f

[Mesa-dev] [PATCH 11/51] glsl: Enable 16-bit texturing in nir-conversion

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/glsl_to_nir.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index c0adf744e0..b16efa6555 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/g

[Mesa-dev] [PATCH 25/51] intel/compiler/fs: Support for combining 16-bit immediates

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_combine_constants.cpp | 84 + 1 file changed, 71 insertions(+), 13 deletions(-) diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp index e0c95d379b..

[Mesa-dev] [PATCH 23/51] intel/compiler: Prepare for 16-bit 3-src ops

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_eu_emit.c | 21 + src/intel/compiler/brw_inst.h | 4 src/intel/compiler/brw_reg_type.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_em

[Mesa-dev] [PATCH 40/51] intel/compiler/fs: Prepare 16-bit and/or/xor for 32-bit src

In GLSL->NIR translation logic operations with boolean typed operands are treated as operating with integer operands. The values of the operands therefore can be 0xFFF/0x000 in case they are produced with 32-bit execution type or 0x/0x in case of 16-bit. This patch allows 16-bit l

[Mesa-dev] [PATCH 28/51] intel/compiler/fs: Use component_size() instead of open coded

This prepares for following patch will add 16-bit tex/fb write payload padding support. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 2 +- src/intel/compiler/brw_fs_copy_propagation.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 24/51] intel/compiler: Add support for negating 16-bit floats

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_shader.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index cc9297772b..3a83f55f28 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/

[Mesa-dev] [PATCH 18/51] intel/compiler: Allow 16-bit math

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 1507968e6c..87b144e871 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/i

[Mesa-dev] [PATCH 34/51] intel/compiler/fs: Pad 16-bit const loads into full regs

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 64243312b9..c455fa4e27 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/

[Mesa-dev] [PATCH 47/51] glsl: HACK: Force texture return into 16-bits

and convert coordinates unconditionally to 32-bits. Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/lower_mediump.cpp | 19 +++ 1 file changed, 19 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 07f1f1ba9d..094ab4

[Mesa-dev] [PATCH 14/51] intel/compiler/fs: Support for dumping 16-bit IMM values

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 694fcc1919..1b972972c1 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -

[Mesa-dev] [PATCH 31/51] intel/compiler/fs: Pad 16-bit output (store/fb write) payloads

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 6d9b272a57..d3125d7dcd 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/in

[Mesa-dev] [PATCH 38/51] intel/compiler/fs: Use original reg size when retyping nir src

In case of boolean typed the values maybe given in 16-bits whereas NIR unconditionally regards them as 32-bit. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/i

[Mesa-dev] [PATCH 26/51] intel/compiler/fs: Set 16-bit sampler return format

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_generator.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 20d018e1fe..610a545cd8 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +

[Mesa-dev] [PATCH 42/51] i965: WIP: Support for uploading 16-bit uniforms from 32-bit store

At this point 16-bit uniforms still take full 32-bit slots in the pull/push constant buffers and in shader deployment payload. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_compiler.h | 9 + src/intel/compiler/brw_fs.cpp | 12 sr

[Mesa-dev] [PATCH 49/51] glsl: HACK: Lower builtin float outputs to 16-bits by default

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/lower_mediump.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 45cf75b53c..bae18c9bfb 100644 --- a/src/compiler/glsl/lower_mediump.cpp +++ b/s

[Mesa-dev] [PATCH 17/51] intel/compiler: Prepare for glsl mediump float uniforms

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_shader.cpp | 13 + src/mesa/drivers/dri/i965/brw_program.c | 10 +- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 234b

[Mesa-dev] [PATCH 43/51] intel/compiler/fs: WIP: Use 32-bit slots for 16-bit uniforms

--- src/intel/compiler/brw_fs_nir.cpp | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2060a3139d..631bbf7f92 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH 50/51] glsl: HACK: Lower all temporary float variables to 16-bits

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/lower_mediump.cpp | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index bae18c9bfb..73b8aa577c 100644 --- a/src/compiler/glsl/lower_mediump.cpp +++ b/s

[Mesa-dev] [PATCH 46/51] glsl: Lower float conversions to mediump

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/lower_mediump.cpp | 26 ++ 1 file changed, 26 insertions(+) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 0276e74d6e..07f1f1ba9d 100644 --- a/src/compiler/glsl/lower_medi

[Mesa-dev] [PATCH 32/51] intel/compiler/fs: Pad 16-bit nir vec* components into full reg

This allows quite a bit of infra to be kept as is, such as liveness analysis, copy propagation and dead code elimination. Here one deals with virtual register space and this doesn't prevent from packing more than one component into one hardware register later on. That is entirely matter of registe

[Mesa-dev] [PATCH 27/51] intel/compiler/fs: Set tex type for generator to flag fp16

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 10 +- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 5751bb0ad7..0d415e2393 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/com

[Mesa-dev] [PATCH 30/51] intel/compiler/fs: Pad 16-bit texture return payloads

This is to tell offset and read/write calculators enough to work correctly with 16-bit texture payloads. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 21 +++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.

[Mesa-dev] [PATCH 39/51] intel/compiler/fs: Consider logic ops on 16-bit booleans

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 70 ++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 2a32b1449a..aff592c354 100644 --- a/src/in

[Mesa-dev] [PATCH 35/51] intel/compiler/fs: Pad 16-bit payload lowering

Otherwise copy propagation fails when write sizes differ. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 5 - src/intel/compiler/brw_ir_fs.h | 13 + 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/com

[Mesa-dev] [PATCH 48/51] glsl: HACK: Treat input varyings as 16-bits by conversion

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/lower_mediump.cpp | 26 +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 094ab4e743..45cf75b53c 100644 --- a/src/compiler/

[Mesa-dev] [PATCH 33/51] intel/compiler/fs: Pad 16-bit nir intrinsic dest into full reg

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index cbb1c118d2..64243312b9 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/in

[Mesa-dev] [PATCH 13/51] intel/compiler/disasm: Print fp16 also for sampler messages

This is what render target write does. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_disasm.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index da2a5d78dd..fbb18b0f26 100644 --- a/src/intel/compiler/brw_d

[Mesa-dev] [PATCH 37/51] intel/compiler/fs: Consider original sizes when retyping alu ops

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 30 -- 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index baa84b0f3c..d28ed57eca 100644 --- a/src/intel/comp

[Mesa-dev] [PATCH 41/51] intel/compiler/eu: Take stride into account in 16-bit ops

This is needed when converting from F -> HF. Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_eu_validate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index 6ee6b4ffbe..735ea6 100644 --- a/src/

[Mesa-dev] [PATCH 15/51] intel/compiler: Add support for loading 16-bit constants

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a973c18203..65a5bfa49a 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compile

[Mesa-dev] [PATCH 51/51] i965/fs: Lower gles mediump floats into 16-bits

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_link.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index d18521e792..89ccbb06b5 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b

[Mesa-dev] [PATCH 44/51] glsl: WIP: Add lowering pass for treating mediump as float16

At least the following need more thought: 1) Converting right-hand-side of assignments from 16-bits to 32-bits - More correct thing to do is to treat rhs as 32-bits latest in the expression producing the value 2) Texture arguments except coordinates are not handled at all - Moreover, c

[Mesa-dev] [PATCH 29/51] intel/compiler/fs: Add register padding support

Signed-off-by: Topi Pohjolainen --- src/intel/compiler/brw_fs.cpp | 3 ++- src/intel/compiler/brw_fs.h| 3 ++- src/intel/compiler/brw_fs_builder.h| 25 ++--- src/intel/compiler/brw_fs_copy_propagation.cpp | 1 + src/intel/com

[Mesa-dev] [PATCH 45/51] glsl: Use 16-bit constants if operation is otherwise 16-bit

Signed-off-by: Topi Pohjolainen --- src/compiler/glsl/lower_mediump.cpp | 43 - 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/src/compiler/glsl/lower_mediump.cpp b/src/compiler/glsl/lower_mediump.cpp index 89eed8b294..0276e74d6e 100644 --- a/sr

Re: [Mesa-dev] [PATCH mesa] compiler: use proper guard for asserts

I ended up looking at all the uses of DEBUG in Mesa, and will send a whole series next week, including more changes in nir & compiler, so you can disregard this patch for now. On Thursday, 2017-11-23 13:24:25 +, Eric Engestrom wrote: > nir_validate.c's #endif already had the correct NDEBUG com

Re: [Mesa-dev] [PATCH 44/51] glsl: WIP: Add lowering pass for treating mediump as float16

On Friday, 2017-11-24 14:27:11 +0200, Topi Pohjolainen wrote: > At least the following need more thought: > > 1) Converting right-hand-side of assignments from 16-bits to 32-bits >- More correct thing to do is to treat rhs as 32-bits latest in the > expression producing the value > > 2)

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On 24 November 2017 at 10:25, Eric Engestrom wrote: > On Thursday, 2017-11-23 11:08:04 -0800, Matt Turner wrote: >> The code defines a macro blk0(i) based on the preprocessor condition >> BYTE_ORDER == LITTLE_ENDIAN. If true, blk0(i) is defined as a byte swap >> operation. Unfortunately, if the pr

Re: [Mesa-dev] [PATCH mesa] st/dri: replace hard-coded array size with ARRAY_SIZE()

Reviewed-by: Marek Olšák Marek On Fri, Nov 24, 2017 at 11:51 AM, Eric Engestrom wrote: > Signed-off-by: Eric Engestrom > --- > Could've sworn I had already seen someone post this patch; guess either > I was mistaken, or it got lost on the way. > --- > src/gallium/state_trackers/dri/dri_screen

[Mesa-dev] [PATCH 4/5] Android: add Wundef to the build flags

From: Emil Velikov The compiler will warns us when we're misusing undefined macros. Note: this will trigger a bunch of warnings, which will be resolved ASAP. Cc: Tapani Pälli Cc: Rob Herring Signed-off-by: Emil Velikov --- Android.common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a

[Mesa-dev] [PATCH 2/5] meson: add Wundef to the build flags

From: Emil Velikov Analogous to the other build systems. Cc: Eric Engestrom Cc: Dylan Baker Signed-off-by: Emil Velikov --- meson.build | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/meson.build b/meson.build index 53013e47ec4..2e704e18c93 100644 --- a/meson.build ++

[Mesa-dev] [PATCH 1/5] configure.ac: add Wundef to the build flags

From: Emil Velikov From the manual: Warn if an undefined identifier is evaluated in an `#if' directive. This is something we want to know and address. Otherwise we can end up with subtle issues, in the less commonly used codepaths. Note: this will trigger a lot of extra warnings, with ~60 of

[Mesa-dev] [PATCH 5/5] Android: copy -fno*math* options from the autotools build

From: Emil Velikov Add -fno-math-errno and -fno-trapping-math to the build. Mesa does not depend on the functionality provided, thus this should result in slightly faster code and smaller binaries. Cc: Tapani Pälli Cc: Rob Herring Signed-off-by: Emil Velikov --- Gents, please do some basic r

[Mesa-dev] [PATCH 3/5] scons: add Wundef to the build flags

From: Emil Velikov Analogous to the other build systems. Cc: Jose Fonseca Cc: Brian Paul Signed-off-by: Emil Velikov --- scons/gallium.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scons/gallium.py b/scons/gallium.py index ef3b2ee81ae..74793a2525c 100755 --- a/scons/gallium.py +++ b

Re: [Mesa-dev] [PATCH 1/5] configure.ac: add Wundef to the build flags

On Friday, 2017-11-24 14:25:02 +, Emil Velikov wrote: > From: Emil Velikov > > From the manual: > Warn if an undefined identifier is evaluated in an `#if' directive. > > This is something we want to know and address. Otherwise we can end up > with subtle issues, in the less commonly used c

[Mesa-dev] [Bug 103868] VK_PRESENT_MODE_MAILBOX_KHR blacks out the whole screen intermittently when using X11 compositing window managers

https://bugs.freedesktop.org/show_bug.cgi?id=103868 --- Comment #4 from Michel Dänzer --- (In reply to Spencer Brown from comment #3) > dmesg > > Nothing really seems interesting to me here. Did you capture it after reproducing the problem as well? This doesn't look directly related to RADV bu

[Mesa-dev] [PATCH] mesa: Add GL4.6 aliases of functions from GL_ARB_indirect_parameters

--- src/mapi/glapi/gen/GL4x.xml | 22 ++ 1 file changed, 22 insertions(+) diff --git a/src/mapi/glapi/gen/GL4x.xml b/src/mapi/glapi/gen/GL4x.xml index 88dba5c..ea28d8e 100644 --- a/src/mapi/glapi/gen/GL4x.xml +++ b/src/mapi/glapi/gen/GL4x.xml @@ -73,6 +73,28 @@ +

[Mesa-dev] [Bug 103868] VK_PRESENT_MODE_MAILBOX_KHR blacks out the whole screen intermittently when using X11 compositing window managers

https://bugs.freedesktop.org/show_bug.cgi?id=103868 --- Comment #5 from Spencer Brown --- Okay, it looks like this doesn't happen with the AMDGPU driver. It's only a problem with modesetting. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for th

[Mesa-dev] [Bug 103868] VK_PRESENT_MODE_MAILBOX_KHR blacks out the whole screen intermittently when using X11 compositing window managers

https://bugs.freedesktop.org/show_bug.cgi?id=103868 Michel Dänzer changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |xorg-t...@lists.x.org

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On Mon, Nov 20, 2017 at 8:11 PM, James Jones wrote: > As many here know at this point, I've been working on solving issues related > to DMA-capable memory allocation for various devices for some time now. I'd > like to take this opportunity to apologize for the way I handled the EGL > stream prop

Re: [Mesa-dev] [PATCH 3/5] scons: add Wundef to the build flags

On 24/11/17 14:25, Emil Velikov wrote: From: Emil Velikov Analogous to the other build systems. Cc: Jose Fonseca Cc: Brian Paul Signed-off-by: Emil Velikov --- scons/gallium.py | 1 + 1 file changed, 1 insertion(+) diff --git a/scons/gallium.py b/scons/gallium.py index ef3b2ee81ae..7479

[Mesa-dev] [Bug 99125] Log to a file all GALLIUM_HUD infos

https://bugs.freedesktop.org/show_bug.cgi?id=99125 --- Comment #3 from Shmerl --- (In reply to Edmondo Tommasina from comment #2) > FYI: Marek pushed the series of patches to mesa git master. > > https://cgit.freedesktop.org/mesa/mesa/commit/ > ?id=3f5fba8a7be61bfc0f46a5ea058108f6e0e1c268 Shoul

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On November 23, 2017 09:00:05 Emil Velikov wrote: Hi James, On 21 November 2017 at 01:11, James Jones wrote: -I have also heard some general comments that regardless of the relationship between GBM and the new allocator mechanisms, it might be time to move GBM out of Mesa so it can be devel

Re: [Mesa-dev] GBM and the Device Memory Allocator Proposals

On November 24, 2017 09:45:07 Jason Ekstrand wrote: On November 23, 2017 09:00:05 Emil Velikov wrote: Hi James, On 21 November 2017 at 01:11, James Jones wrote: -I have also heard some general comments that regardless of the relationship between GBM and the new allocator mechanisms, it m

[Mesa-dev] [Bug 103814] incorrect dust rendering in hl2 without sisched

https://bugs.freedesktop.org/show_bug.cgi?id=103814 Hleb Valoshka <375...@gmail.com> changed: What|Removed |Added Summary|incorrect dust rendering in |incorrect dust renderi

Re: [Mesa-dev] [PATCH 1/3] util: Fix SHA1 implementation on big endian

On Fri, 2017-11-24 at 13:32 +, Emil Velikov wrote: > On 24 November 2017 at 10:25, Eric Engestrom > wrote: > > On Thursday, 2017-11-23 11:08:04 -0800, Matt Turner wrote: > > > The code defines a macro blk0(i) based on the preprocessor condition > > > BYTE_ORDER == LITTLE_ENDIAN. If true, blk0

[Mesa-dev] [PATCH mesa 01/16] c99_{compat, math}.h: check for macro existance before using it

Fixes thousands of warnings when using -Wundef, which is about to land, as these two files are included virtually everywhere. Signed-off-by: Eric Engestrom --- include/c99_compat.h | 6 +++--- include/c99_math.h | 5 +++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/include/

[Mesa-dev] [PATCH mesa 03/16] radv: tie radv_assert() enablement to regular assert()

Signed-off-by: Eric Engestrom --- src/amd/vulkan/radv_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index addd35e5ce10fa37bd3f..327ce5415947abc1712d 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/a

[Mesa-dev] [PATCH mesa 05/16] amd/addrlib: remove duplicate definition of ADDR_DBG_BREAK()

It's already defined above (around line 60). Signed-off-by: Eric Engestrom --- src/amd/addrlib/core/addrcommon.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h index 99bb62e77f446f912d35..80ea0eb247aa48dcb176 100644 ---

[Mesa-dev] [PATCH mesa 04/16] amd: remove always-true BRAHMA_BUILD define

Signed-off-by: Eric Engestrom --- src/amd/Android.addrlib.mk | 2 -- src/amd/Makefile.addrlib.am | 3 +-- src/amd/addrlib/core/addrcommon.h| 15 ++- src/amd/addrlib/meson.build | 2 +- src/gallium/winsys/amdgpu/drm/Android.mk | 4 +--

[Mesa-dev] [PATCH mesa 02/16] anv: tie anv_assert() enablement to regular assert()

Signed-off-by: Eric Engestrom --- src/intel/vulkan/anv_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 6d4e43f2e687cbf26ccd..6474abf0f3694c7fcd3a 100644 --- a/src/intel/vulkan/anv_private.h +++ b/s

[Mesa-dev] [PATCH mesa 07/16] amd/addrlib: use NDEBUG to guard asserts

Signed-off-by: Eric Engestrom --- src/amd/addrlib/core/addrelemlib.cpp | 2 +- src/amd/addrlib/core/addrlib1.cpp| 8 src/amd/addrlib/core/addrlib2.h | 2 +- src/amd/addrlib/gfx9/gfx9addrlib.cpp | 4 ++-- src/amd/addrlib/r800/egbaddrlib.cpp | 2 +- 5 files changed, 9 insertions(

[Mesa-dev] [PATCH mesa 10/16] vc4: check preprocessor token existence using #ifdef instead of #if

(other uses of USE_VC4_SIMULATOR are already correct) Signed-off-by: Eric Engestrom --- src/gallium/drivers/vc4/vc4_screen.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/vc4/vc4_screen.c b/src/gallium/drivers/vc4/vc4_screen.c index a42ba675c130c2

[Mesa-dev] [PATCH mesa 14/16] util/cache: use NDEBUG to guard asserts

Signed-off-by: Eric Engestrom --- src/gallium/auxiliary/util/u_cache.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/auxiliary/util/u_cache.c b/src/gallium/auxiliary/util/u_cache.c index c748cb99dd0c468f4342..f14ba97996873a716aff 100644 --- a/src/gallium

[Mesa-dev] [PATCH mesa 09/16] amd/addrlib: add comment about breakpoint not working in some cases

Signed-off-by: Eric Engestrom --- src/amd/addrlib/core/addrcommon.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/addrlib/core/addrcommon.h b/src/amd/addrlib/core/addrcommon.h index 1a7473a4d33c1271f077..9261c5890903d0dc1c0b 100644 --- a/src/amd/addrlib/core/addrcom

[Mesa-dev] [PATCH mesa 06/16] amd/addrlib: fix macro test

Check macro existence instead of relying on the compiler turning undef into 0. Signed-off-by: Eric Engestrom --- src/amd/addrlib/core/addrlib1.cpp | 2 +- src/amd/addrlib/r800/egbaddrlib.cpp | 4 ++-- src/amd/addrlib/r800/siaddrlib.cpp | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-)

[Mesa-dev] [PATCH mesa 11/16] broadcom: use NDEBUG to guard asserts

Signed-off-by: Eric Engestrom --- src/broadcom/cle/v3d_packet_helpers.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/broadcom/cle/v3d_packet_helpers.h b/src/broadcom/cle/v3d_packet_helpers.h index c86cad85266f503dbeba..bc1bf3eb76ec94aff16d 100644 --- a/src/b

[Mesa-dev] [PATCH mesa 12/16] compiler: use NDEBUG to guard asserts

nir_validate.c's #endif already had the correct NDEBUG comment Fixes: dcb1acdea00a8f2c29777 "nir/validate: Only build in debug mode" Fixes: 9ff71b649b4b3808a9e17 "i965/nir: Validate that NIR passes call nir_metadata_preserve()" Signed-off-by: Eric Engestrom --- src/compiler/nir/nir.h |

[Mesa-dev] [PATCH mesa 13/16] compiler: fix typo

Signed-off-by: Eric Engestrom --- src/compiler/nir/nir_lower_io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c index 3879f0297d3959e720ff..df91febd68dd1f5fa7af 100644 --- a/src/compiler/nir/nir_lower_io.c +++

[Mesa-dev] [PATCH mesa 08/16] amd/addrlib: fix DEBUG guards

Use the normal `#ifdef` style used by the rest of Mesa, instead of sometimes locally defining DEBUG on non-debug builds and then relying on the precompiler converting #undef'ed macros to 0 when checking. Signed-off-by: Eric Engestrom --- I would argue this block should go, as all it does is enabl

[Mesa-dev] [PATCH mesa 16/16] util: use NDEBUG to guard asserts

Signed-off-by: Eric Engestrom --- src/util/ralloc.c | 18 +- src/util/slab.c | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/util/ralloc.c b/src/util/ralloc.c index 42cfa2e391d52df68db2..b52079ac075a0fe11944 100644 --- a/src/util/ralloc.c +++ b/sr

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