The symbol 'enum intel_miptree_create_flags' is used there but it is
defined at 'intel_mipmap_tree.h', which is not included. This is causing
a compile warning.
---
src/mesa/drivers/dri/i965/intel_tex.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_tex.h
b/sr
---
src/gallium/drivers/i915/i915_fpc_translate.c | 16
1 file changed, 16 deletions(-)
diff --git a/src/gallium/drivers/i915/i915_fpc_translate.c
b/src/gallium/drivers/i915/i915_fpc_translate.c
index a9601e82ca9..2eaa1e64ef7 100644
--- a/src/gallium/drivers/i915/i915_fpc_transl
On Thu, Aug 24, 2017 at 4:07 PM, Tomasz Figa wrote:
> Hi everyone,
>
> On Sat, Aug 19, 2017 at 8:52 AM, Emil Velikov
> wrote:
>> On 14 August 2017 at 19:42, Jason Ekstrand wrote:
>>> I missed the stable CC when I pushed this one. It needs to be in 17.2
>>>
>> Ack, queued up.
>
> Thanks for the
Reviewed-by: Eduardo Lima Mitev
Thanks, Ken
Eduardo
On 08/25/2017 08:40 AM, Kenneth Graunke wrote:
> We were using brw->gen, brw->is_haswell, and devinfo->gen in a few
> places, when we could just use GEN_GEN and GEN_IS_HASWELL, which are
> evaluated at compile time.
> ---
> src/mesa/drivers/d
Hi Dieter,
sorry for the churn -- do these issues also occur with the latest
addition to https://cgit.freedesktop.org/~nh/mesa/log/?h=tgsi-const-2d?
Cheers,
Nicolai
On 25.08.2017 08:19, Dieter Nützel wrote:
Am 25.08.2017 07:38, schrieb Dieter Nützel:
Am 23.08.2017 18:41, schrieb Nicolai Häh
On 08/24/2017 04:24 PM, Ilia Mirkin wrote:
> On Thu, Aug 24, 2017 at 9:54 AM, Alejandro Piñeiro
> wrote:
>> From: Eduardo Lima Mitev
>>
>> Adds new INT16, UINT16 and FLOAT16 base types.
>>
>> The corresponding GL types for half floats were reused from the
>> AMD_gpu_shader_half_float extension.
On Fri, Aug 25, 2017 at 12:48:22AM -0400, Ilia Mirkin wrote:
> The rest should be possible too, just needs some additional
> investigation. Passes fbo-*-formats piglit tests.
Reviewed-by: Wladimir J. van der Laan
> Signed-off-by: Ilia Mirkin
> ---
> src/gallium/drivers/freedreno/a2xx/fd2_gmem.
Hi,
On 25.08.2017 00:30, Kenneth Graunke wrote:
On Thursday, August 24, 2017 4:16:39 AM PDT kevin.rogo...@intel.com wrote:
From: Kevin Rogovin
Special thanks to Eero Tamminen for reporting rasterizer
numbers being twice what it should be for 2xMSAA under
a benchmark.
Signed-off-by: Kevin Rog
Am Donnerstag, den 24.08.2017, 20:00 -0300 schrieb Fabio Estevam:
> Hi,
>
> Getting the following errors when running glmark2 terrain test on imx6q:
>
> # glmark2-es2-drm -b terrain
> ** Failed to set swap interval. Results may be bounded above by refresh rate.
> =
On 24/08/17 21:07, Connor Abbott wrote:
>
> Hi Alejandro,
Hi Connor,
>
> This seems really suspicious. If the live ranges are really
> independent, then the register allocator should be able to assign the
> two virtual registers to the same physical register if it needs to.
Yes, it is true, the
Am Freitag, den 25.08.2017, 10:20 +0900 schrieb Michel Dänzer:
> On 25/08/17 02:38 AM, Gert Wollny wrote:
> >
> > The patch doesn't introduce piglit regression (I tested the shader
> > subset).
>
> I'd recommend testing at least the gpu profile, ideally running on X.
I've done that now running
On 25/08/17 05:30 PM, Gert Wollny wrote:
> Am Freitag, den 25.08.2017, 10:20 +0900 schrieb Michel Dänzer:
>> On 25/08/17 02:38 AM, Gert Wollny wrote:
>>>
>>> The patch doesn't introduce piglit regression (I tested the shader
>>> subset).
>>
>> I'd recommend testing at least the gpu profile, ideall
On 08/25/2017 02:36 AM, Timothy Arceri wrote:
On 24/08/17 23:21, Samuel Pitoiset wrote:
Signed-off-by: Samuel Pitoiset
---
src/mesa/main/transformfeedback.c | 49
---
1 file changed, 30 insertions(+), 19 deletions(-)
diff --git a/src/mesa/main/transfo
On Thursday, 2017-08-24 14:52:14 -0400, Adam Jackson wrote:
> The snprintf stuff here already constructs the right name for the device
> node, and if it doesn't, you configured Mesa wrong, don't do that.
Very good point.
Reviewed-by: Eric Engestrom
>
> Signed-off-by: Adam Jackson
> ---
> src/
Am Donnerstag, 24. August 2017, 16:39:58 CEST schrieben Sie:
> On 24 August 2017 at 15:26, Marc Dietrich wrote:
> > Hi Elie,
> >
> > Am Mittwoch, 23. August 2017, 13:07:30 CEST schrieb Elie Tournier:
> >> From: Elie Tournier
> >>
> >> TL;DR
> >> This series is a "status update" of my work done
Hi Eric,
I'm working on lima gp compiler which should benefit from nir lowering
uniform load to scalar.
I notice you write the nir_lower_io_to_scalar.c which support lowering
shader_in/shader_out
but left the uniform lowering in vc4 driver, any reason why not
implement in the nir_lower_io_to_scala
The include I added in 688d866eca isn't actually useful, as it only
declares the opaque struct ANativeWindow. provides the
contents of the struct, which is what is needed by platform_android.
Fixes: 688d866eca8943f09cd8 "egl/android: add missing include"
Cc: Chih-Wei Huang
Cc: Rob Herring
Signe
On 25/08/17 19:22, Samuel Pitoiset wrote:
On 08/25/2017 02:36 AM, Timothy Arceri wrote:
On 24/08/17 23:21, Samuel Pitoiset wrote:
Signed-off-by: Samuel Pitoiset
---
src/mesa/main/transformfeedback.c | 49
---
1 file changed, 30 insertions(+), 19 deletio
Found by code inspection.
Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs")
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/dr
The first email updates the calendar with a proposal for the future
releases until the end of 2017. It also removes versions that have
already been released.
The second patch is a proposal to add yet another final iteration to
the 17.1 cycle.
Andres Gomez (2):
docs: remove released and extend t
Completed the 17.2 cycle and added the beginning of the 17.3 one.
Cc: Emil Velikov
Cc: Juan A. Suarez Romero
Signed-off-by: Andres Gomez
---
docs/release-calendar.html | 86 ++
1 file changed, 80 insertions(+), 6 deletions(-)
diff --git a/docs/relea
Cc: Emil Velikov
Cc: Juan A. Suarez Romero
Signed-off-by: Andres Gomez
---
docs/release-calendar.html | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index 1ed3ae14a97..011e37a6765 100644
--- a/docs/release-calen
Nicolai,
Have you thought about switching to NIR for radeonsi completely to get
16-bit support? We need NIR support anyway for spirv, right? Would be it be
easier than adding 16-bit support into TGSI, glsl2tgsi, and tgsi2llvm?
Marek
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e.g. 0 + 32 <= 32 should be valid.
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
---
src/amd/vulkan/radv_cmd_buffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index cbe0de17db
On Friday, 2017-08-25 13:39:05 +0200, Christian Gmeiner wrote:
> Found by code inspection.
>
> Fixes: c9e8b49b885 ("etnaviv: gallium driver for Vivante GPUs")
> Cc: mesa-sta...@lists.freedesktop.org
> Signed-off-by: Christian Gmeiner
Good catch!
Reviewed-by: Eric Engestrom
> ---
> src/gallium
On Fri, 2017-08-25 at 14:40 +0300, Andres Gomez wrote:
> The first email updates the calendar with a proposal for the future
> releases until the end of 2017. It also removes versions that have
> already been released.
>
> The second patch is a proposal to add yet another final iteration to
> the
On Friday, 2017-08-25 14:40:25 +0300, Andres Gomez wrote:
> Completed the 17.2 cycle and added the beginning of the 17.3 one.
>
> Cc: Emil Velikov
> Cc: Juan A. Suarez Romero
> Signed-off-by: Andres Gomez
> ---
> docs/release-calendar.html | 86
> ++
Thanks Bas!
This fixes CTS
dEQP-VK.pipeline.vertex_input.max_attributes.32_attributes.binding_one_to_one.interleaved
Tested-by: Samuel Pitoiset
On 08/25/2017 02:15 PM, Bas Nieuwenhuizen wrote:
e.g. 0 + 32 <= 32 should be valid.
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulk
Hi Lucas,
On Fri, Aug 25, 2017 at 4:57 AM, Lucas Stach wrote:
> There is no fix for this. The terrain shaders are simply too big to be
> executed on GC2000. (You remember that 512 instruction limit mentioned
> in the reference manual? That's it.)
>
> This demo runs fine on GC3000.
Thanks for th
On 24 August 2017 at 19:52, Adam Jackson wrote:
> The snprintf stuff here already constructs the right name for the device
> node, and if it doesn't, you configured Mesa wrong, don't do that.
>
I think the idea was that "snprintf can fail" even though in practise
it will never do.
In all fairness
From: Marek Olšák
The discard range codepath takes precedence, so if we get both
unsynchronized and discard_range, choose unsynchronized.
---
src/gallium/auxiliary/util/u_threaded_context.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/util/u_thread
From: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 4 ++--
src/gallium/auxiliary/util/u_threaded_context.h | 4 ++--
src/gallium/drivers/radeon/r600_buffer_common.c | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_c
This will allow to propagate VK_ERROR_OUT_OF_HOST_MEMORY to
vkEndCommandBuffer() when necessary.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 16
src/amd/vulkan/radv_private.h| 2 +-
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/src
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 23 ---
1 file changed, 16 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 21e2dfd9f7..cc9aeafefa 100644
--- a/src/amd/vulkan/radv_cmd_bu
v2: - store record_result in radv_CmdBeginRenderPass()
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 24 +---
1 file changed, 17 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 21e2d
From: Nicolai Hähnle
Fixes: 420c438589c8 ("radeonsi: log draw and compute state into log context")
---
src/gallium/drivers/radeonsi/si_debug.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/rad
From: Nicolai Hähnle
The data is read when the render_cond_atom is emitted, so we must
delay emitting the atom until after the flush.
Fixes: 0fe0320dc074 ("radeonsi: use optimal packet order when doing a pipeline
sync")
---
src/gallium/drivers/radeon/r600_pipe_common.h | 3 ++-
src/gallium/dr
From: Nicolai Hähnle
The result written by the shader workaround needs to be written back, or
the CP may read stale data.
Fixes: 78476cfe071a ("radeonsi: enable ARB_transform_feedback_overflow_query")
---
src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
src/gallium/drivers/radeon/r600_q
On 25.08.2017 13:58, Marek Olšák wrote:
Nicolai,
Have you thought about switching to NIR for radeonsi completely to get
16-bit support? We need NIR support anyway for spirv, right? Would be it
be easier than adding 16-bit support into TGSI, glsl2tgsi, and tgsi2llvm?
Well. What's missing from
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 22 --
1 file changed, 16 insertions(+), 6 del
When reallocation for encoder
v2: use deinterlace common function
v3: make sure deinterlace only
v4: bail out when reallocation for interlaced buffer
Signed-off-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 25 -
1 file changed, 20 insertions(+), 5 deletions
On 08/24/2017 02:48 PM, Leo Liu wrote:
On 08/24/2017 11:34 AM, Christian König wrote:
Am 24.08.2017 um 17:11 schrieb Leo Liu:
Signed-off-by: Leo Liu
Reviewed-by: Christian König for the series.
Andy do you want to test this? Should make VA-API transcoding simpler
to use.
Just got ch
On Fri, Aug 25, 2017 at 10:50 AM, Nicolai Hähnle wrote:
> On 25.08.2017 13:58, Marek Olšák wrote:
>>
>> Nicolai,
>>
>> Have you thought about switching to NIR for radeonsi completely to get
>> 16-bit support? We need NIR support anyway for spirv, right? Would be it be
>> easier than adding 16-bit
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu
---
src/gallium/state_trackers/va/picture.c | 22 --
On Fri, 2017-08-25 at 09:08 +0300, Tapani Pälli wrote:
> On 08/24/2017 01:12 PM, Juan A. Suarez Romero wrote:
> > This structure contains two fields, binding and index, that store
> > the
> > binding in the descriptor set and the index inside the binding.
> >
> > These structures are defined as ui
This structure contains two fields, binding and index, that store the
binding in the descriptor set and the index inside the binding.
These structures are defined as uint8_t, but the types in Vulkan
specification are uint32_t, so big values are clamp.
This fixes
dEQP-VK.binding_model.shader_acce
Reviewed-by: Emil Velikov
-Emil
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On 24 August 2017 at 15:22, Eric Engestrom wrote:
> On Thursday, 2017-08-24 08:54:04 -0500, Rob Herring wrote:
>> On Thu, Aug 24, 2017 at 7:49 AM, Eric Engestrom
>> wrote:
>> > Khronos: https://github.com/KhronosGroup/EGL-Registry/pull/22
>> > Cc: Rob Herring
>> > Cc: Emil Velikov
>> > Signed-o
Reviewed-by: Emil Velikov
Thanks
Emil
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On 25 August 2017 at 12:40, Andres Gomez wrote:
> Completed the 17.2 cycle and added the beginning of the 17.3 one.
>
> Cc: Emil Velikov
> Cc: Juan A. Suarez Romero
> Signed-off-by: Andres Gomez
> ---
> docs/release-calendar.html | 86
> ++
> 1 file
On Aug 25, 2017 4:10 PM, "Matt Turner" wrote:
On Fri, Aug 25, 2017 at 10:50 AM, Nicolai Hähnle wrote:
> On 25.08.2017 13:58, Marek Olšák wrote:
>>
>> Nicolai,
>>
>> Have you thought about switching to NIR for radeonsi completely to get
>> 16-bit support? We need NIR support anyway for spirv, rig
Leo Liu wrote:
v2: use deinterlace common function
v3: make sure deinterlace only
Doesn't apply to master with git.
patch was less fussy
patch -p 1 < ~/Leo-va-interl-patches/02-3
patching file src/gallium/state_trackers/va/picture.c
Hunk #1 succeeded at 619 with fuzz 1 (offset 6 lines).
Hunk
On Thu, 2017-08-24 at 23:27 -0700, Kenneth Graunke wrote:
> > diff --git a/src/glx/glxextensions.h b/src/glx/glxextensions.h
> > index 21ad02a44b..2a595516ee 100644
> > --- a/src/glx/glxextensions.h
> > +++ b/src/glx/glxextensions.h
> > @@ -101,6 +101,7 @@ enum
> > GL_ARB_texture_env_combine_b
On 08/25/2017 12:42 PM, Andy Furniss wrote:
Leo Liu wrote:
v2: use deinterlace common function
v3: make sure deinterlace only
Doesn't apply to master with git.
I will attach you another one. should be good. Too much patches on the fly.
Thanks,
Leo
patch was less fussy
patch -p 1 < ~
Am 24.08.2017 um 20:40 schrieb Adam Jackson:
> The only difference from the EXT version is bumping the minmax to 16, so
> just hit all the drivers at once.
>
> v2: Fix driver names, add to 17.3 release notes (Ilia Mirkin)
>
> Reviewed-by: Ilia Mirkin
> Signed-off-by: Adam Jackson
> ---
> docs/
Signed-off-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_uvd.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 228f654af1..00d6267018 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
Signed-off-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 648a493b59..228f654af1 100644
--- a/src/gallium/drivers/radeon/radeon_uvd
Alejandro Piñeiro writes:
> Although it is possible to emit them directly as AND/OR on brw_fs_nir,
> having specific opcodes makes it easier to remove duplicate settings
> later.
>
> Signed-off-by: Alejandro Piñeiro
> Signed-off-by: Jose Maria Casanova Crespo
> ---
> src/intel/compiler/brw_e
On Tue, Aug 22, 2017 at 2:15 PM, Nicolai Hähnle wrote:
> On 22.08.2017 14:10, Nicolai Hähnle wrote:
>>
>> On 22.08.2017 13:00, Marek Olšák wrote:
>>>
>>> On Tue, Aug 22, 2017 at 9:37 AM, Nicolai Hähnle
>>> wrote:
On 18.08.2017 19:06, Marek Olšák wrote:
>
>
> Ping.
>
Alejandro Piñeiro writes:
> On 24/08/17 21:07, Connor Abbott wrote:
>>
>> Hi Alejandro,
>
> Hi Connor,
>
>>
>> This seems really suspicious. If the live ranges are really
>> independent, then the register allocator should be able to assign the
>> two virtual registers to the same physical registe
https://bugs.freedesktop.org/show_bug.cgi?id=102038
--- Comment #17 from Brad King ---
After applying the two patches I can confirm that the VTK test I used to
produce the apitrace now passes again. Thanks!
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You are receiving this mail because:
You are the QA Contact for the bug.
You are the
We didn't allow them before because it didn't look like the spec allowed
it. It certainly doesn't make much sense. However, there are CTS tests
that apparently hit this. What the spec actually says is:
"Importing a payload using handle types with copy transference
creates a duplicate co
It only applies to legacy BO fences.
---
src/intel/vulkan/anv_batch_chain.c | 2 +-
src/intel/vulkan/anv_private.h | 10 +-
src/intel/vulkan/anv_queue.c | 24
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_cha
This adds the DRM_SYNCOBJ_CREATE_SIGNALED flag as well as the ioctls:
- DRM_IOCTL_SYNCOBJ_WAIT
- DRM_IOCTL_SYNCOBJ_RESET
- DRM_IOCTL_SYNCOBJ_SIGNAL
---
include/drm-uapi/drm.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/include/drm-uapi/drm.h b/include/drm-uapi/d
---
src/intel/vulkan/anv_gem.c | 62
src/intel/vulkan/anv_gem_stubs.c | 20 +
src/intel/vulkan/anv_private.h | 5
3 files changed, 87 insertions(+)
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 9bd37f4
This is just a refactor, similar to what we did for semaphores, in
preparation for handling VK_KHR_external_fence.
---
src/intel/vulkan/anv_batch_chain.c | 22 --
src/intel/vulkan/anv_private.h | 42 ++-
src/intel/vulkan/anv_queue.c | 144 ++-
---
src/intel/vulkan/anv_gem.c | 28 +
src/intel/vulkan/anv_gem_stubs.c | 13 ++
src/intel/vulkan/anv_private.h | 4 +++
src/intel/vulkan/anv_queue.c | 53 +++-
4 files changed, 87 insertions(+), 11 deletions(-)
diff --g
---
src/intel/vulkan/anv_gem.c | 4 ++--
src/intel/vulkan/anv_gem_stubs.c | 2 +-
src/intel/vulkan/anv_private.h | 2 +-
src/intel/vulkan/anv_queue.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/anv_gem.c b/src/intel/vulkan/anv_gem.c
index 57a
---
src/vulkan/util/vk_alloc.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/vulkan/util/vk_alloc.h b/src/vulkan/util/vk_alloc.h
index 2915021..f58a806 100644
--- a/src/vulkan/util/vk_alloc.h
+++ b/src/vulkan/util/vk_alloc.h
@@ -37,6 +37,20 @@ vk_alloc(const VkAllocationC
---
src/intel/vulkan/anv_wsi.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_wsi.c b/src/intel/vulkan/anv_wsi.c
index 9369f26..00edb22 100644
--- a/src/intel/vulkan/anv_wsi.c
+++ b/src/intel/vulkan/anv_wsi.c
@@ -364,22 +364,25 @@ VkResult anv_Get
---
src/intel/vulkan/anv_batch_chain.c | 19 -
src/intel/vulkan/anv_extensions.py | 5 ++
src/intel/vulkan/anv_queue.c | 142 -
3 files changed, 161 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/a
This commit changes fences to work a bit more like BO semaphores.
Instead of the fence being a batch, it's simply a BO that gets added
to the validation list for the last execbuf call in the QueueSubmit
operation. It's a bit annoying finding the last submit in the execbuf
but this allows us to avo
In order to implement VK_KHR_external_fence, we need to back our fences
with something that's shareable. Since the kernel wait interface for
sync objects already supports waiting for multiple fences in one go, it
makes anv_WaitForFences much simpler if we only have one type of fence.
---
src/inte
Qiang Yu writes:
> Hi Eric,
>
> I'm working on lima gp compiler which should benefit from nir lowering
> uniform load to scalar.
> I notice you write the nir_lower_io_to_scalar.c which support lowering
> shader_in/shader_out
> but left the uniform lowering in vc4 driver, any reason why not
> impl
https://bugs.freedesktop.org/show_bug.cgi?id=102017
--- Comment #17 from Thomas Jollans ---
Thanks everyone for looking into this. I can confirm that the issue was a
missing libtxc_dxtn for me too.
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You are receiving this mail because:
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Am 25.08.2017 um 17:15 schrieb Leo Liu:
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed-off-by: Leo Liu
---
src/gallium/state_trackers
On Fri, Aug 25, 2017 at 8:42 PM, Marek Olšák wrote:
> On Tue, Aug 22, 2017 at 2:15 PM, Nicolai Hähnle wrote:
>> On 22.08.2017 14:10, Nicolai Hähnle wrote:
>>>
>>> On 22.08.2017 13:00, Marek Olšák wrote:
On Tue, Aug 22, 2017 at 9:37 AM, Nicolai Hähnle
wrote:
>
> On 18.08.20
On 08/25/2017 03:16 PM, Christian König wrote:
Am 25.08.2017 um 17:15 schrieb Leo Liu:
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterlace only
Signed
Accompanying patch "st/mesa: only try to create 1x msaa surfaces for
'fake' msaa" requires driver to report max_samples=1 to enable "fake"
msaa. Previously, 0 and 1 were treated equivalently in st_init_extensions()
and either could enable "fake" msaa.
This patch raises the swr default msaa_max_cou
From: Brian Paul
For software drivers where we want "fake" msaa support for GL 3.x, we
treat 1 sample as being msaa.
For drivers with real msaa support, start format probing at 2x msaa.
For drivers with fake msaa support, start format probing at 1x msaa.
This also tweaks the MaxSamples code in
Leo Liu wrote:
On 08/25/2017 03:16 PM, Christian König wrote:
Am 25.08.2017 um 17:15 schrieb Leo Liu:
On 08/25/2017 10:53 AM, Leo Liu wrote:
On 08/25/2017 02:57 AM, Christian König wrote:
Am 24.08.2017 um 20:49 schrieb Leo Liu:
v2: use deinterlace common function
v3: make sure deinterl
+ }
Should we bail out with an error here when it's the other way
around?
Although I cannot think of any of case that to get buffer
Interlaced now, It's still a good idea to bail out here when it
happnens
Will add it in v4.
It's not a error when case like buffer is deinterlaced, an
From: Emil Velikov
Inlining the implementation does not cause additional overhead in
terms of build time while the binary is increased only marginally (~1k)
At the same time the compiler should be able to optimise better, although
this is not a path where we'll notice much difference.
Use a loc
From: Emil Velikov
Originally required for the u_vector implementation, which was inlined
in u_vector.h with previous commit.
Using libmesautil pulled the C++ runtime (string_to_uint_map.cpp),
which is something don't want to impose in our libEGL.
We could consider rewriting string_to_uint_map
If we merge a mapping with the mapping before it, we also need
to not only change the offset, but also the bo offset.
Fixes: 715df30a4e2 "radv/amdgpu: Add winsys implementation of virtual buffers."
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 1 +
1 file changed, 1 insertion(+)
diff --git
On Fri, 2017-08-25 at 14:41 +0100, Emil Velikov wrote:
> Should we drop the "if (n != -1 && n < sizeof(buf))" part as well with
> this patch?
Meh. I've got some other changes coming in the area so that'll probably
happen soon anyway. At least for this change I just wanted to make
things determini
Leo Liu wrote:
+ }
Should we bail out with an error here when it's the other
way around?
Although I cannot think of any of case that to get buffer
Interlaced now, It's still a good idea to bail out here
when it happnens Will add it in v4.
It's not a error when case like buffer is de
Hello list,
The candidate for the Mesa 17.1.8 is now available. Currently we have:
- 15 queued
- 0 nominated (outstanding)
- and 2 rejected patches
In the current queue we have:
In Mesa Core we include a fix to prevent a crash in
glCompressedTextureSubImage3D.
The GLSL compiler now includes
On August 25, 2017 12:14:20 PM Eric Anholt wrote:
Qiang Yu writes:
Hi Eric,
I'm working on lima gp compiler which should benefit from nir lowering
uniform load to scalar.
I notice you write the nir_lower_io_to_scalar.c which support lowering
shader_in/shader_out
but left the uniform lowerin
On Fri, Aug 25, 2017 at 1:20 PM, Emil Velikov
wrote:
> From: Emil Velikov
>
> Originally required for the u_vector implementation, which was inlined
> in u_vector.h with previous commit.
>
> Using libmesautil pulled the C++ runtime (string_to_uint_map.cpp),
> which is something don't want to imp
On 26/08/17 00:50, Nicolai Hähnle wrote:
On 25.08.2017 13:58, Marek Olšák wrote:
Nicolai,
Have you thought about switching to NIR for radeonsi completely to get
16-bit support? We need NIR support anyway for spirv, right? Would be
it be easier than adding 16-bit support into TGSI, glsl2tgsi
otherwise the result might contain random data.
fixes on nvc0:
* KHR-GL45.pipeline_statistics_query_tests_ARB.functional_default_qo_values
*
KHR-GL45.pipeline_statistics_query_tests_ARB.functional_non_rendering_commands_do_not_affect_queries
Signed-off-by: Karol Herbst
Cc: mesa-sta...@lists.f
Why is this necessary? If data is not initialized, then presumably
pipe->get_query_result will have returned false.
On Fri, Aug 25, 2017 at 7:15 PM, Karol Herbst wrote:
> otherwise the result might contain random data.
>
> fixes on nvc0:
> * KHR-GL45.pipeline_statistics_query_tests_ARB.functiona
On Fri, Aug 25, 2017 at 7:37 PM, Karol Herbst wrote:
> On Sat, Aug 26, 2017 at 1:30 AM, Ilia Mirkin wrote:
>> Why is this necessary? If data is not initialized, then presumably
>> pipe->get_query_result will have returned false.
>>
>
> but it didn't. It might be the drivers fault (in my case nouv
https://bugs.freedesktop.org/show_bug.cgi?id=102377
--- Comment #4 from Bruce Cherniak ---
The proposed patch looks good. Regressions with the 4BYTE_ALIGNED_ONLY caps
set are fixed.
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On Sat, Aug 26, 2017 at 1:38 AM, Ilia Mirkin wrote:
> On Fri, Aug 25, 2017 at 7:37 PM, Karol Herbst wrote:
>> On Sat, Aug 26, 2017 at 1:30 AM, Ilia Mirkin wrote:
>>> Why is this necessary? If data is not initialized, then presumably
>>> pipe->get_query_result will have returned false.
>>>
>>
>>
On 25 August 2017 at 23:25, Jason Ekstrand wrote:
> On Fri, Aug 25, 2017 at 1:20 PM, Emil Velikov
> wrote:
>>
>> From: Emil Velikov
>>
>> Originally required for the u_vector implementation, which was inlined
>> in u_vector.h with previous commit.
>>
>> Using libmesautil pulled the C++ runtime (
---
src/intel/compiler/brw_eu_emit.c | 22 ++
src/intel/compiler/brw_inst.h| 21 +
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index e4fcbe908d..f1a2283de8 100644
--
I'm going to call this from brw_inst.h, and I don't want to have to
include all of brw_reg.h.
---
src/intel/compiler/brw_reg.h | 13 -
src/intel/compiler/brw_reg_type.h | 15 +++
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/intel/compiler/brw_re
---
src/intel/compiler/brw_disasm.c | 12 ---
src/intel/compiler/brw_inst.h | 4 +--
src/intel/compiler/brw_reg_type.c | 76 ---
src/intel/compiler/brw_reg_type.h | 7 ++--
4 files changed, 79 insertions(+), 20 deletions(-)
diff --git a/src/intel/co
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