Jason Ekstrand writes:
> On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> wrote:
>
>> Alternatively we could have extended the current semantics to 32-wide
>> mode by changing brw_broadcast() to emit multiple indexed MOV
>> instructions in the generator copying the selected value to all
>> de
On 05/24/2016 04:58 PM, Kristian Høgsberg wrote:
> From: Kristian Høgsberg Kristensen
>
> As per GL_KHR_robustness, we have to return GL_CONTEXT_LOST from all
> entry points when we lose a context. We do this by creating a new
> dispatch table and setting that when we learn that we've lost the
>
Jason Ekstrand writes:
> On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> wrote:
>
>> Due to a Gen7-specific hardware bug native 32-wide instructions get
>> the lower 16 bits of the execution mask applied incorrectly to both
>> halves of the instruction, so the MOV trick we currently use woul
On Tuesday, May 24, 2016 5:27:59 PM PDT Francisco Jerez wrote:
> Jason Ekstrand writes:
>
> > On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
> > wrote:
> >
> >> Due to a Gen7-specific hardware bug native 32-wide instructions get
> >> the lower 16 bits of the execution mask applied incorrectly
Print "GEOM" instead of "2", for example.
v2: also update the text parsing code, per Ilia.
---
src/gallium/auxiliary/tgsi/tgsi_dump.c | 3 +++
src/gallium/auxiliary/tgsi/tgsi_text.c | 22 ++
2 files changed, 25 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_dump.
---
src/gallium/auxiliary/tgsi/tgsi_strings.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.h
b/src/gallium/auxiliary/tgsi/tgsi_strings.h
index 031d322..9a9362e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.h
+++ b/src/gallium/a
On Tue, May 17, 2016 at 11:50:28AM -0700, Matt Turner wrote:
> On Mon, May 16, 2016 at 4:27 PM, Ardinartsev Nikita
> wrote:
> > Fixes regression introduced by af5ca43f2676bff7499f93277f908b681cb821d0
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95419
>
> Thank you very much for the
Kenneth Graunke writes:
> On Tuesday, May 24, 2016 5:27:59 PM PDT Francisco Jerez wrote:
>> Jason Ekstrand writes:
>>
>> > On Tue, May 24, 2016 at 12:18 AM, Francisco Jerez
>> > wrote:
>> >
>> >> Due to a Gen7-specific hardware bug native 32-wide instructions get
>> >> the lower 16 bits of the
Jason Ekstrand writes:
> Does this mean we can delete the field from brw_fs_generator?
>
Almost, there is still one use left in fire_fb_write() (for the dual
source blend last-rt hack) which we will be able to get rid of
eventually, but it cannot simply be replaced with inst->exec_size
because it
On Tue, May 24, 2016 at 4:58 PM, Kristian Høgsberg wrote:
> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
> b/src/mesa/drivers/dri/i965/intel_extensions.c
> index feea6ca..b8d7517 100644
> --- a/src/mesa/drivers/dri/i965/intel_extensions.c
> +++ b/src/mesa/drivers/dri/i965/intel_exten
On Tuesday, May 24, 2016 1:37:46 AM PDT Jordan Justen wrote:
> In d8347f12ead89c5a58f69ce9283a54ac8487159c, we added support for
> skipping SIMD8 generation when the program local size is too large for
> SIMD8 to be usable. This change was missed in that commit.
>
> This bug would impact gen7 plat
On Tue, May 17, 2016 at 06:39:02PM +0100, Plamena Manolova wrote:
> eglCreatePbufferSurface should generate an EGL_BAD_MATCH error if:
> 1: The EGL_TEXTURE_FORMAT attribute is EGL_NO_TEXTURE and EGL_TEXTURE_TARGET
> is something other than EGL_NO_TEXTURE
> 2: EGL_TEXTURE_FORMAT is something other t
On Tue, May 24, 2016 at 6:04 PM, Matt Turner wrote:
> On Tue, May 24, 2016 at 4:58 PM, Kristian Høgsberg wrote:
>> diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
>> b/src/mesa/drivers/dri/i965/intel_extensions.c
>> index feea6ca..b8d7517 100644
>> --- a/src/mesa/drivers/dri/i965/intel
On Tue, May 24, 2016 at 5:22 PM, Ilia Mirkin wrote:
> Sorry to be pedantic, but you're enabling the ext for gles1.1, but the new
> entrypoint appear to only apply to gles2. I think you also want a es1="1.1"
> or something along those lines.
The extension requires 2.0, so maybe we should instead o
From: Kristian Høgsberg Kristensen
GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry
points that we already implement. This patch adds a new dispatch
table that returns GL_CONTEXT_LOST from all entry points and
implements the GL_LOSE_CONTEXT_ON_RESET by setting that table when
On May 24, 2016 10:25 PM, "Kristian Høgsberg" wrote:
>
> On Tue, May 24, 2016 at 5:22 PM, Ilia Mirkin wrote:
> > Sorry to be pedantic, but you're enabling the ext for gles1.1, but the
new
> > entrypoint appear to only apply to gles2. I think you also want a
es1="1.1"
> > or something along those
On Tue, May 24, 2016 at 5:01 PM, Jason Ekstrand wrote:
> The buffer_range_* arrays are indexed by buffer index not element index.
Reviewed-by: Kristian Høgsberg
> ---
> src/mesa/drivers/dri/i965/brw_draw_upload.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/sr
On Tue, May 24, 2016 at 7:47 PM, Ilia Mirkin wrote:
>
> On May 24, 2016 10:25 PM, "Kristian Høgsberg" wrote:
>>
>> On Tue, May 24, 2016 at 5:22 PM, Ilia Mirkin wrote:
>> > Sorry to be pedantic, but you're enabling the ext for gles1.1, but the
>> > new
>> > entrypoint appear to only apply to gles
Series is
Reviewed-by: Ilia Mirkin
On Tue, May 24, 2016 at 8:43 PM, Brian Paul wrote:
> Print "GEOM" instead of "2", for example.
>
> v2: also update the text parsing code, per Ilia.
> ---
> src/gallium/auxiliary/tgsi/tgsi_dump.c | 3 +++
> src/gallium/auxiliary/tgsi/tgsi_text.c | 22
There are a number of packing tests already in piglit but I have a few
more on the way.
This series does not add support for doubles as there is currently a
doubles bug with explicit locations that I've pointed out to the Igalia
guys. Samuel is working on a fix for this after which I will finish
u
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 38 +++-
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index ce61898..e0d88c6 100644
--- a/src/mesa/drivers/dri/i965/brw_
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 21 +
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index d5d7a77..b5a4fc8 100644
--- a/sr
---
src/compiler/nir/nir.h| 4 ++--
src/compiler/nir/nir_lower_io.c | 25 -
src/mesa/drivers/dri/i965/brw_nir.c | 12 +++-
src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 +++
4 files changed, 36 insertions(+), 8 deletions(-)
dif
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 17 +++--
src/mesa/drivers/dri/i965/brw_fs.h | 5 +++--
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 29 -
3 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.c
This will be used to store the total number of components used at this location
when packing via ARB_enhanced_layouts.
---
src/compiler/glsl/ir.h | 5 +++
src/compiler/glsl/link_varyings.cpp | 74 -
src/compiler/glsl/linker.cpp| 2 +
src/c
Here we add a new param to the type_size functions in order to pass
in the size of a varying once packing is taken into account.
---
src/compiler/nir/nir.h | 6 +++--
src/compiler/nir/nir_lower_io.c| 35 +-
src/mesa/drivers/dri/i965/
---
docs/GL3.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index 2dff3cd..edc04a1 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -193,11 +193,11 @@ GL 4.4, GLSL 4.40:
GL_MAX_VERTEX_ATTRIB_STRIDE DONE (all drive
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index e0d88c6..51da3bd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/m
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a19ece7..16fd7d6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b
This offset is used for packing.
---
src/compiler/nir/nir.h| 6 ++
src/compiler/nir/nir_intrinsics.h | 8
src/compiler/nir/nir_lower_io.c | 8
3 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 7
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 33
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 51da3bd..a19ece7 100644
--- a/src/mesa/drivers/dri/i965/brw_
---
src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index feea6ca..5d831e5 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/
On Tue, May 24, 2016 at 10:41 PM, Kristian Høgsberg wrote:
> From: Kristian Høgsberg Kristensen
>
> GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry
> points that we already implement. This patch adds a new dispatch
> table that returns GL_CONTEXT_LOST from all entry points an
On 25.05.2016 09:09, Mike Lothian wrote:
> Do you need the DRM version number if you'll be displaying the kernel
> version anyway?
Yes, because the DRM version depends on the kernel driver being used.
The patch is
Reviewed-by: Michel Dänzer
--
Earthling Michel Dänzer |
On Tuesday, May 24, 2016 17:42:17 Roland Scheidegger wrote:
> Am 24.05.2016 um 08:41 schrieb mathias.froehl...@gmx.net:
> > From: Mathias Fröhlich
> >
> > The aim is to replace the CoordReplace array by
> > a bitfield. Until all drivers are converted,
> > establish the bitfield in paralell to the
Hi Brian,
On Tuesday, May 24, 2016 11:29:56 Brian Paul wrote:
> On 05/24/2016 12:41 AM, mathias.froehl...@gmx.net wrote:
> > From: Mathias Fröhlich
> >
> > Hi all,
> >
> > following a series with performance improvements
> > for cpu/draw bound applications. This part makes
> > more use of the bit
On Tue, May 24, 2016 at 8:19 PM, Ilia Mirkin wrote:
> On Tue, May 24, 2016 at 10:41 PM, Kristian Høgsberg
> wrote:
>> From: Kristian Høgsberg Kristensen
>>
>> GL_KHR_robustness adds the GL_CONTEXT_LOST error and five new entry
>> points that we already implement. This patch adds a new dispatch
From: Dave Airlie
According to GL4.5 spec:
An INVALID_OPERATION error is generated if any part of the speci-
fied buffer range is mapped with MapBufferRange or MapBuffer (see sec-
tion 6.3), unless it was mapped with MAP_PERSISTENT_BIT set in the Map-
BufferRange access flags.
So we should use t
On Tue, May 24, 2016 at 7:48 PM, Kristian Høgsberg
wrote:
> On Tue, May 24, 2016 at 5:01 PM, Jason Ekstrand
> wrote:
> > The buffer_range_* arrays are indexed by buffer index not element index.
>
> Reviewed-by: Kristian Høgsberg
>
Thanks!
> > ---
> > src/mesa/drivers/dri/i965/brw_draw_uploa
From: Kristian Høgsberg Kristensen
Signed-off-by: Kristian Høgsberg Kristensen
---
src/compiler/.gitignore | 4
src/compiler/nir/tests/.gitignore| 1 +
src/mesa/drivers/dri/i965/.gitignore | 3 +++
src/util/.gitignore | 1 +
src/util/tests/hash_table/.giti
> Sure. Unfortunately, the series does not apply cleanly on ToT master:
>
> % git am p[12].txt
> Applying: scons: whitespace cleanup
> Using index info to reconstruct a base tree...
> error: patch failed: src/gallium/state_trackers/wgl/SConscript:12
> error: src/gallium/state_trackers/wgl/SConscri
On Tue, May 24, 2016 at 9:07 PM, Kristian Høgsberg wrote:
> From: Kristian Høgsberg Kristensen
>
> Signed-off-by: Kristian Høgsberg Kristensen
> ---
> src/compiler/.gitignore | 4
> src/compiler/nir/tests/.gitignore| 1 +
> src/mesa/drivers/dri/i965/.gitignore | 3 +++
> s
Reviewed-by: Tobias Klausmann
On 25.05.2016 01:59, Ilia Mirkin wrote:
Signed-off-by: Ilia Mirkin
---
This addresses the feedback I got after pushing the enablement patch.
docs/relnotes/11.3.0.html | 1 +
src/compiler/glsl/builtin_variables.cpp | 10 --
src/compile
https://bugs.freedesktop.org/show_bug.cgi?id=96176
Bug ID: 96176
Summary: Cannot build non-intel drivers without python3.
Product: Mesa
Version: git
Hardware: x86-64 (AMD64)
OS: All
Status: NEW
Keywords: b
https://bugs.freedesktop.org/show_bug.cgi?id=95529
--- Comment #3 from Vladislav Egorov ---
Yes, they look washed out or half-transparent. Checker pattern is not a part of
the bug, Wikipedia uses it as a background. Trace:
https://www.dropbox.com/s/dusvloqxwi2iuj6/chrome.1.trace
--
You are rece
On Tue, May 24, 2016 at 12:46 AM, Marek Olšák wrote:
> On Mon, May 23, 2016 at 10:47 PM, Giuseppe Bilotta
> wrote:
>> On Mon, May 23, 2016 at 4:45 PM, Marek Olšák wrote:
>>> I think it would be better to put stuff like this only into the
>>> renderer string of drivers which use LLVM. The majorit
This should be enough to get the FS generator emitting 32-wide code
for at least compute shaders. Most of the work in this series is
about fixing the current codegen infrastructure to support arbitrary
channel group controls and execution sizes (other than dispatch_width
that is), and extending se
This implements some simple helper functions that can be used to
specify the group of channel enable signals and compression enable
that apply to a brw_inst instruction.
It's intended to replace brw_set_default_compression_control
eventually because the current interface has a number of shortcomin
By using the new compression/group control interface. This will allow
easier extension to support arbitrary channel enable groups at the IR
level.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 44 ++
1 file changed, 17 insertions(+), 27 deletions(-)
diff --git a/sr
p->compressed won't work for SIMD32, we should just be using the
execution size value specified via p->current instead.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 24 +++-
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
Most of these are bugs because the intended execution size of an
instruction and the dispatch width of the shader aren't necessarily
the same (especially in SIMD32 programs).
---
src/mesa/drivers/dri/i965/brw_eu.h | 1 -
src/mesa/drivers/dri/i965/brw_eu_emit.c| 3 +--
src/mes
From: Kenneth Graunke
Curro is planning to eliminate p->compressed, so let's avoid using it
here and just pass in the value directly.
Signed-off-by: Kenneth Graunke
[ Francisco Jerez: Pass boolean flag instead of brw_compression enum. ]
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i9
This was kind of an abuse of p->compressed, dataport send message
instructions are always uncompressed. Use the current execution size
instead since p->compressed is on its way out.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
d
---
src/mesa/drivers/dri/i965/brw_eu.c | 5 -
src/mesa/drivers/dri/i965/brw_eu.h | 1 -
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 +-
3 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drive
This generalizes the current fs_inst::force_sechalf flag to allow
specifying channel enable groups other than 0 or 8. At some point it
will likely make sense to fix the vec4 generator to support arbitrary
execution groups and then move the definition of fs_inst::group into
backend_instruction (e.g
The hardware has messages that can write 32 32bit components at once
but the channel enable mask gets messed up. We need to split them
into several 16-wide scratch writes for the channel enables to be
applied correctly. The SIMD lowering pass cannot be used for this
because scratch writes are emi
In SIMD32 programs the compiler is responsible for providing the
appropriate half of the sample mask in the message header, so the
first and third quarters both map to the first slot group of the
provided 16-bit half, while the second and fourth quarters map to the
second slot group -- IOW they sho
Instead of just halving the execution size when the instruction is
compressed hoping that it will give a legal source region width, we
can calculate the maximum legal width value in closed form from the
component size and stride. This makes sure that brw_reg_from_fs_reg()
always returns a valid ha
This makes FIND_LIVE_CHANNEL behave like a normal instruction for
non-zero quarter control. On Gen8+ we just leave the quarter control
field of the emitted FBL instruction set to the default value so the
hardware applies the expected shift to the execution mask signals. On
Gen7 we apply the offse
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 31 ++-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 4 +++
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 +--
3 files changed, 18 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw
Trivial clean-up.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8828e2b..a1cb5c2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.
Due to a Gen7-specific hardware bug native 32-wide instructions get
the lower 16 bits of the execution mask applied incorrectly to both
halves of the instruction, so the MOV trick we currently use wouldn't
work. Instead emit multiple 16-wide MOV instructions in 32-wide mode
in order to cover the w
Alternatively we could have extended the current semantics to 32-wide
mode by changing brw_broadcast() to emit multiple indexed MOV
instructions in the generator copying the selected value to all
destination registers, but it seemed rather silly to waste EU cycles
unnecessarily copying the exact sa
Most of these were resetting quarter control to zero incorrectly even
though everything they needed to do was disable instruction
compression -- The brw_SAMPLE() case was doing the right thing but it
can be simplified slightly by using the new compression control
interface.
---
src/mesa/drivers/dr
We don't want to emit a 32-wide send message in 32-wide programs. The
memory fence message should have the same effect regardless of the
execution size (as long as it's valid) so just set it to one.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 11 +++
1 file changed, 7 insertions(+), 4 d
This gets IF and DO instructions working in SIMD32 programs. brw_IF()
and brw_DO() should probably behave in the same way as other generator
functions that emit control flow instructions and just figure out the
right execution size by themselves from the current execution controls
specified throug
The right value is dependent on the specific IR instruction being
generated so it has to be reset in every iteration of the loop anyway.
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mes
Gen7 hardware expects the block size field in the message descriptor
to be the number of registers minus one instead of the log2 of the
number of registers.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965
On Friday, May 20, 2016 5:05:03 PM PDT Juan A. Suarez Romero wrote:
> For double-precision vertex inputs we need to measure them in dvec4
> terms, and for single-precision vertex inputs we need to measure them in
> vec4 terms.
>
> For the later case, we use type_size_vec4() function. For the forme
On Tue, May 24, 2016 at 2:26 AM, Emil Velikov wrote:
> On 23 May 2016 at 22:11, Giuseppe Bilotta wrote:
>> I'll try. I've never used scons before thought so I might need some
>> guidance along the way. (Doubly so considering that trying to run
>>
>> % scons
>>
>> on my work dir results in a backt
On 20.05.2016 19:23, Marek Olšák wrote:
> From: Marek Olšák
This series is
Reviewed-by: Michel Dänzer
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
_
The idea sounds good to me, but this (1U << i) needs consistency in my
opinion. It's correct and avoid some compiler warnings (if the
corresponding flags are used) but we currently don't do that.
I would suggest to keep the (1 << i) for now, and maybe make a separate
patch which replaces 1 by
If not, mesa building fails with the following errors:
/mesa/src/gbm/../../include/c11/threads_posix.h:189: undefined reference to
`pthread_mutexattr_init'
/mesa/src/gbm/../../include/c11/threads_posix.h:190: undefined reference to
`pthread_mutexattr_settype'
/mesa/source/mesa/src/gbm/../../inclu
We added this support into nir for Mesa's Intel vulkan driver as part
of the SPIR-V support, so we can use it for the i965 driver as well.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_compiler.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_
In d8347f12ead89c5a58f69ce9283a54ac8487159c, we added support for
skipping SIMD8 generation when the program local size is too large for
SIMD8 to be usable. This change was missed in that commit.
This bug would impact gen7 platforms when the compute shader local
size is greater than 512, and gen8
Signed-off-by: Jordan Justen
---
src/compiler/nir/nir.c | 4
src/compiler/nir/nir.h | 2 ++
src/compiler/nir/nir_gather_info.c | 1 +
src/compiler/nir/nir_intrinsics.h | 1 +
src/compiler/nir/nir_lower_system_values.c | 16
git://people.freedesktop.org/~jljusten/mesa hsw-cs-cross-thread-constants-v1
Note: These patches break the anv (vulkan) build. In the branch above
branch I have a hack patch which will build anv, but anv will be
broken. (Ie, I need to add another 'squash' patch for anv to this
series.)
These patc
Signed-off-by: Jordan Justen
---
src/compiler/glsl/builtin_variables.cpp | 13 +++--
src/compiler/glsl/glsl_parser_extras.cpp | 8
src/mesa/drivers/dri/i965/brw_compiler.c | 2 ++
src/mesa/main/mtypes.h | 4
src/mesa/state_tracker/st_extensions.c | 4
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
src/mesa/drivers/dri/i965/brw_nir.h| 1 +
src/mesa/drivers/dri/i965/brw_nir_intrinsics.c | 142 +
3 files changed, 144 insertions(+)
create mode 100644 src/mesa/drivers/
Signed-off-by: Jordan Justen
---
src/compiler/nir/nir_intrinsics.h| 1 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +
2 files changed, 14 insertions(+)
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index aeb6038..6f86c9f 100644
--- a
This pass replaces the local id and local index intrinsics with i965
specific nir code.
It relies on the gl_i965_cs_thread_local_id uniform variable which
actually varies per thread to provide a thread local id.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_nir.c | 1 +
1 file
This thread ID will be used to compute the gl_LocalInvocationIndex and
gl_LocalInvocationID values.
Signed-off-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_compiler.h | 1 +
src/mesa/drivers/dri/i965/brw_cs.c | 16 +---
src/mesa/drivers/dri/i965/brw_fs.cpp
The old method pushed data for each channels uvec3 data of
gl_LocalInvocationID.
The new method pushes 1 dword of data that is a 'thread local ID'
value. Based on that value, we can generate gl_LocalInvocationIndex
and gl_LocalInvocationID with some simple calculations.
Signed-off-by: Jordan Just
We need information about push constants in two state atoms, so we
calculated roughly the same information twice.
When we add support for uploading both a common (cross-thread) set of
push constants, combined with the previous per-thread push constant
data, things are going to get even more compli
The cross thread constant support appears on Haswell. It allows us to
upload a set of uniform data for all threads without duplicating it
per thread.
We also support per-thread data which allows us to store a per-thread
ID in one of the uniforms that can be used to calculate the
gl_LocalInvocation
The main patch is the second, the first is just a cleanup of EOL whitespace.
Giuseppe Bilotta (2):
scons: whitespace cleanup
scons: support 2.5.0
SConstruct| 4 ++--
scons/custom.py | 9 -
src/gallium/SConscript
---
SConstruct| 4 ++--
src/gallium/SConscript| 2 +-
src/gallium/auxiliary/SConscript | 10 +-
src/gallium/drivers/svga/SConscript | 2 +-
src/gallium/state_trackers/wgl/SConscript | 2 +-
src/gallium/targets/libgl-gdi
The get_implicit_deps changed in SCons 2.5, expecting a callable rather
than a path as third argument. Detect the SCons versions and set the
argument appropriately to support both 2.5 and earlier versions.
This closes #95211.
---
scons/custom.py | 9 -
1 file changed, 8 insertions(+), 1 d
On 24 May 2016 at 09:21, Alejandro Piñeiro wrote:
> If not, mesa building fails with the following errors:
> /mesa/src/gbm/../../include/c11/threads_posix.h:189: undefined reference to
> `pthread_mutexattr_init'
> /mesa/src/gbm/../../include/c11/threads_posix.h:190: undefined reference to
> `pth
On 24/05/16 10:58, Emil Velikov wrote:
> On 24 May 2016 at 09:21, Alejandro Piñeiro wrote:
>> If not, mesa building fails with the following errors:
>> /mesa/src/gbm/../../include/c11/threads_posix.h:189: undefined reference to
>> `pthread_mutexattr_init'
>> /mesa/src/gbm/../../include/c11/thre
From: Emil Velikov
Add weak symbol notation for the pthread_mutexattr* symbols, thus making
the linker happy. When building with -O1 or greater the optimiser will
kick in and remove the said functions as they are dead/unreachable code.
Ideally we'll enable the optimisations locally, yet that doe
[Adding Jose]
On 24 May 2016 at 09:43, Giuseppe Bilotta wrote:
> The get_implicit_deps changed in SCons 2.5, expecting a callable rather
> than a path as third argument. Detect the SCons versions and set the
> argument appropriately to support both 2.5 and earlier versions.
>
> This closes #95211
On Tue, May 24, 2016 at 2:13 PM, Emil Velikov wrote:
> [Adding Jose]
[Wait, I thought I did? Or did I get the email address wrong?
> On 24 May 2016 at 09:43, Giuseppe Bilotta wrote:
>> This closes #95211.
> For the future please use the full URL.
Ack. Sorry, used to LibreOffice where one can j
On Tue, May 24, 2016 at 4:57 AM, Emil Velikov wrote:
> From: Emil Velikov
>
> Add weak symbol notation for the pthread_mutexattr* symbols, thus making
> the linker happy. When building with -O1 or greater the optimiser will
> kick in and remove the said functions as they are dead/unreachable code
On Tue, May 24, 2016 at 9:06 AM, Rob Herring wrote:
> On Tue, May 24, 2016 at 4:57 AM, Emil Velikov
> wrote:
>> From: Emil Velikov
>>
>> Add weak symbol notation for the pthread_mutexattr* symbols, thus making
>> the linker happy. When building with -O1 or greater the optimiser will
>> kick in
On Tue, May 24, 2016 at 9:15 AM, Rob Herring wrote:
> On Tue, May 24, 2016 at 8:09 AM, Ilia Mirkin wrote:
>> On Tue, May 24, 2016 at 9:06 AM, Rob Herring wrote:
>>> On Tue, May 24, 2016 at 4:57 AM, Emil Velikov
>>> wrote:
From: Emil Velikov
Add weak symbol notation for the pthr
On Tue, May 24, 2016 at 8:09 AM, Ilia Mirkin wrote:
> On Tue, May 24, 2016 at 9:06 AM, Rob Herring wrote:
>> On Tue, May 24, 2016 at 4:57 AM, Emil Velikov
>> wrote:
>>> From: Emil Velikov
>>>
>>> Add weak symbol notation for the pthread_mutexattr* symbols, thus making
>>> the linker happy. Whe
On Tue, May 24, 2016 at 9:17 AM, Ilia Mirkin wrote:
> On Tue, May 24, 2016 at 9:15 AM, Rob Herring wrote:
>> On Tue, May 24, 2016 at 8:09 AM, Ilia Mirkin wrote:
>>> On Tue, May 24, 2016 at 9:06 AM, Rob Herring wrote:
On Tue, May 24, 2016 at 4:57 AM, Emil Velikov
wrote:
> From: E
Hi Emil,
On 05/21/2016 11:20 AM, Emil Velikov wrote:
> Hi Stan,
>
> First, thanks for re-spinning these according to my suggestions.
Thanks for the comments!
>
> On 20 May 2016 at 12:17, Stanimir Varbanov
> wrote:
>> Push offset down to drivers when importing dmabuf. This is needed
>> to mor
Hi curro,
Am 24.05.2016 um 09:18 schrieb Francisco Jerez:
> This implements some simple helper functions that can be used to
> specify the group of channel enable signals and compression enable
> that apply to a brw_inst instruction.
>
> It's intended to replace brw_set_default_compression_control
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