Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/compiler/nir/nir_intrinsics.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/src/compiler/nir/nir_intrinsics.h
b/src/compiler/nir/nir_intrinsics.h
index aeb6038..6f86c9f 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -304,6 +304,7 @@ SYSTEM_VALUE(work_group_id, 3, 0, xx, xx, xx)
SYSTEM_VALUE(user_clip_plane, 4, 1, UCP_ID, xx, xx)
SYSTEM_VALUE(num_work_groups, 3, 0, xx, xx, xx)
SYSTEM_VALUE(helper_invocation, 1, 0, xx, xx, xx)
+SYSTEM_VALUE(channel_num, 1, 0, xx, xx, xx)
/*
* Load operations pull data from some piece of GPU memory. All load
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index f28583c..6c1e3d2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3881,6 +3881,19 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld,
nir_intrinsic_instr *instr
break;
}
+ case nir_intrinsic_load_channel_num: {
+ const fs_builder bld8 = bld.group(8, 0);
+ fs_reg word_channels = bld.vgrf(BRW_REGISTER_TYPE_UW);
+ dest = retype(dest, BRW_REGISTER_TYPE_UD);
+ bld8.MOV(word_channels, brw_imm_v(0x76543210));
+ if (dispatch_width > 8)
+ bld8.ADD(byte_offset(word_channels, 16), word_channels,
brw_imm_uw(8u));
+ bld.MOV(dest, word_channels);
+ if (dispatch_width > 16)
+ unreachable("Support SIMD32 for channel_num is missing");
+ break;
+ }
+
default:
unreachable("unknown intrinsic");
}
--
2.8.1
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