On Thu, 2015-04-16 at 12:16 -0700, Eric Anholt wrote:
> Eric Anholt writes:
>
> > Jason Ekstrand writes:
> >
> >> On Sat, Apr 11, 2015 at 4:25 PM, Thomas Helland
> >> wrote:
> >>> The performance numbers (shader-db runtime) are:
> >>>
> >>> Difference at 95.0% confidence
> >>> -14.7608 +/
Hi all,
Last year I spent a whole bunch of time profiling Mesa looking for areas
where improvements could be made. Anyway I thought I'd point out a
couple of things, and see if anyone thinks these are worthwhile
following up.
1. While the hash table has been getting a lot of attention lately,
aft
https://bugs.freedesktop.org/show_bug.cgi?id=90073
Bug ID: 90073
Summary: Leaks in xcb_dri3_open_reply_fds() and
get_render_node_from_id_path_tag
Product: Mesa
Version: unspecified
Hardware: Other
OS: All
https://bugs.freedesktop.org/show_bug.cgi?id=90073
--- Comment #1 from Guillaume Desmottes
---
Created attachment 115155
--> https://bugs.freedesktop.org/attachment.cgi?id=115155&action=edit
dri3_open: don't leak the reply
--
You are receiving this mail because:
You are the QA Contact for th
https://bugs.freedesktop.org/show_bug.cgi?id=90073
--- Comment #2 from Guillaume Desmottes
---
Created attachment 115156
--> https://bugs.freedesktop.org/attachment.cgi?id=115156&action=edit
loader: don't leak udev_enumerate
--
You are receiving this mail because:
You are the QA Contact for
On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
> Previously, this function returned the number of elements for structures
> and arrays and 0 for everything else. In NIR, this is almost never what
> you want because we also treat matricies as arrays so you have to
> special-case constantly
On Fri, Apr 17, 2015 at 9:03 AM, Rob Clark wrote:
> On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
>> Previously, this function returned the number of elements for structures
>> and arrays and 0 for everything else. In NIR, this is almost never what
>> you want because we also treat matr
https://bugs.freedesktop.org/show_bug.cgi?id=90073
Signed-off-by: Guillaume Desmottes
---
src/loader/loader.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 17bf133..ec3b278 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -24
https://bugs.freedesktop.org/show_bug.cgi?id=90073
Signed-off-by: Guillaume Desmottes
---
src/glx/dri3_glx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 1ddc723..7a853c6 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1679,6 +1
Signed-off-by: Connor Abbott
---
src/mesa/main/.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/main/.gitignore b/src/mesa/main/.gitignore
index 8256ad7..b5f786d 100644
--- a/src/mesa/main/.gitignore
+++ b/src/mesa/main/.gitignore
@@ -9,3 +9,4 @@ get_hash.h.tmp
format_info
Signed-off-by: Connor Abbott
---
After this, `git status' reports a clean working directory again.
.gitignore | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitignore b/.gitignore
index 00e3ce3..21aa35c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -45,3 +45,4 @@ manifest.txt
.libs/
Makefi
Of course, these commit messages should be swapped... d'oh! Fixed locally.
On Fri, Apr 17, 2015 at 12:59 PM, Connor Abbott wrote:
> Signed-off-by: Connor Abbott
> ---
> src/mesa/main/.gitignore | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/main/.gitignore b/src/mesa/main/.gi
On Fri, Apr 17, 2015 at 9:59 AM, Connor Abbott wrote:
> Signed-off-by: Connor Abbott
> ---
> src/mesa/main/.gitignore | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/main/.gitignore b/src/mesa/main/.gitignore
> index 8256ad7..b5f786d 100644
> --- a/src/mesa/main/.gitignore
> ++
On Fri, Apr 17, 2015 at 1:17 PM, Matt Turner wrote:
> On Fri, Apr 17, 2015 at 9:59 AM, Connor Abbott wrote:
>> Signed-off-by: Connor Abbott
>> ---
>> src/mesa/main/.gitignore | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/src/mesa/main/.gitignore b/src/mesa/main/.gitignore
>> index
On Fri, Apr 17, 2015 at 6:06 AM, Rob Clark wrote:
> On Fri, Apr 17, 2015 at 9:03 AM, Rob Clark wrote:
>> On Fri, Apr 10, 2015 at 8:48 PM, Jason Ekstrand wrote:
>>> Previously, this function returned the number of elements for structures
>>> and arrays and 0 for everything else. In NIR, this is
On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> The BSpec says this applies to Gen6 as well.
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 2 +-
> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/sr
On Thu, Apr 16, 2015 at 2:52 PM, Brian Paul wrote:
> ---
> src/mesa/main/shader_query.cpp | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
> index b5f1d08..ad936e5 100644
> --- a/src/mesa/main/shader_query.cpp
> +++ b/src/mes
On Thu, Apr 16, 2015 at 2:52 PM, Brian Paul wrote:
> If an app called glTextureBarrierNV() without checking if the
> extension was available, we'd crash with some gallium drivers
> in st_TextureBarrier() because the pipe_context::texture_barrier()
> pointer was NULL.
>
> Generate GL_INVALID_OPERAT
On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> In a few commits, we'll start emitting an add(32) instruction on some
> platforms.
> ---
> src/mesa/drivers/dri/i965/brw_eu_emit.c| 2 +-
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 7 ++-
> 2 files changed, 3 insertions(+),
Reviewed-by: Jason Ekstrand
On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> LINTERP's src0 is PLN's src1, and PLN's src1 reads exec_size / 4
> registers.
>
> Having that information lets us drop the delta_x/y special case code in
> split_virtual_grfs().
> ---
> src/mesa/drivers/dri/i965/b
Signed-off-by: Tobias Nygren
---
src/gallium/auxiliary/util/u_network.c | 9 ++---
src/gallium/auxiliary/util/u_network.h | 3 ++-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_network.c
b/src/gallium/auxiliary/util/u_network.c
index 45b3691..a54
Signed-off-by: Tobias Nygren
---
src/gallium/include/pipe/p_config.h | 2 +-
src/mesa/drivers/dri/common/xmlconfig.c | 2 +-
src/mesa/x86/common_x86.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/include/pipe/p_config.h
b/src/gallium/includ
Signed-off-by: Tobias Nygren
---
configure.ac | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 6ccf3b4..325b936 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1641,7 +1641,7 @@ if test "x$enable_nine" = xyes; then
if ! echo "$with_galliu
On Fri, Apr 17, 2015 at 11:13 AM, Jason Ekstrand wrote:
> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>> The BSpec says this applies to Gen6 as well.
>> ---
>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 2 +-
>> src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 4 ++--
>> 2 fi
On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> This lets SIMD16 programs on G45 and Gen5 use the PLN instruction.
This patch also changes the meaning of FS_OPCODE_LINTERP. Those
chainges should be described in the commit message as well.
> On Ironlake:
>
> total instructions in shared pr
On Fri, Apr 17, 2015 at 11:25 AM, Jason Ekstrand wrote:
> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>> In a few commits, we'll start emitting an add(32) instruction on some
>> platforms.
>> ---
>> src/mesa/drivers/dri/i965/brw_eu_emit.c| 2 +-
>> src/mesa/drivers/dri/i965/brw_f
On Fri, Apr 17, 2015 at 11:40 AM, Matt Turner wrote:
> On Fri, Apr 17, 2015 at 11:13 AM, Jason Ekstrand wrote:
>> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>>> The BSpec says this applies to Gen6 as well.
>>> ---
>>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 2 +-
>>> src/me
On Fri, Apr 17, 2015 at 11:45 AM, Jason Ekstrand wrote:
> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>> This lets SIMD16 programs on G45 and Gen5 use the PLN instruction.
>
> This patch also changes the meaning of FS_OPCODE_LINTERP. Those
> chainges should be described in the commit mes
On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can
> calculate them together with a single add(32) instruction on some
> platforms like Broadwell and newer or in SIMD8 elsewhere.
>
> Note that I also moved the PIXEL_X/PIXEL
On Friday, April 17, 2015 11:45:57 AM Jason Ekstrand wrote:
> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> > This lets SIMD16 programs on G45 and Gen5 use the PLN instruction.
>
> This patch also changes the meaning of FS_OPCODE_LINTERP. Those
> chainges should be described in the commi
On Fri, Apr 17, 2015 at 11:56 AM, Matt Turner wrote:
> On Fri, Apr 17, 2015 at 11:45 AM, Jason Ekstrand wrote:
>> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>>> This lets SIMD16 programs on G45 and Gen5 use the PLN instruction.
>>
>> This patch also changes the meaning of FS_OPCODE_LINT
On Fri, Apr 17, 2015 at 11:56 AM, Jason Ekstrand wrote:
> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>> The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can
>> calculate them together with a single add(32) instruction on some
>> platforms like Broadwell and newer or in
On Fri, Apr 17, 2015 at 11:58 AM, Matt Turner wrote:
> On Fri, Apr 17, 2015 at 11:56 AM, Jason Ekstrand wrote:
>> On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
>>> The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can
>>> calculate them together with a single add(32) inst
On Tue, Apr 14, 2015 at 4:15 PM, Matt Turner wrote:
> We don't want to set compression control on a SIMD16 instruction
> operating on words or smaller.
PRM/bspec quote please
> ---
> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> d
I've made a few small comments. One more thing that I'd like to see
is if you could hack up a patch on top to force SIMD8 and do a jenkins
run with that as well. I'm a little nervous about how invasive the
change is. With that done and the 2 or 3 comments addressed, the
series is
Reviewed-by: J
On Fri, Apr 17, 2015 at 11:58 AM, Jason Ekstrand wrote:
> On Fri, Apr 17, 2015 at 11:56 AM, Matt Turner wrote:
>> static inline struct brw_reg
>> offset(struct brw_reg reg, unsigned delta)
>> {
>>reg.nr += delta;
>>return reg;
>> }
>>
>> Presumably you're thinking of offset(fs_reg, unsign
On Fri, Apr 17, 2015 at 12:02 PM, Matt Turner wrote:
> On Fri, Apr 17, 2015 at 11:58 AM, Jason Ekstrand wrote:
>> On Fri, Apr 17, 2015 at 11:56 AM, Matt Turner wrote:
>>> static inline struct brw_reg
>>> offset(struct brw_reg reg, unsigned delta)
>>> {
>>>reg.nr += delta;
>>>return reg;
Thanks.
Acked-by: Matt Turner
and pushed.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Thanks.
Reviewed-by: Matt Turner
and pushed.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Updated numbers look a lot better!
On Tue, Mar 17, 2015 at 4:23 PM, Matt Turner wrote:
> Without NIR:
>
> total instructions in shared programs: 6190374 -> 6190153 (-0.00%)
> instructions in affected programs: 61126 -> 60905 (-0.36%)
> helped:156
total instruc
On Tue, Mar 17, 2015 at 4:23 PM, Matt Turner wrote:
> Without NIR:
>
> total instructions in shared programs: 6190153 -> 6185918 (-0.07%)
> instructions in affected programs: 185156 -> 180921 (-2.29%)
> helped:918
total instructions in shared programs: 6191130
What made the difference here?
On Fri, Apr 17, 2015 at 1:56 PM, Matt Turner wrote:
> Updated numbers look a lot better!
>
> On Tue, Mar 17, 2015 at 4:23 PM, Matt Turner wrote:
>> Without NIR:
>>
>> total instructions in shared programs: 6190374 -> 6190153 (-0.00%)
>> instructions in affected pr
On Fri, Apr 17, 2015 at 2:02 PM, Jason Ekstrand wrote:
> What made the difference here?
I think it's probably just that
commit 4dacb212fdcc82def02b8c9233f94caa5a8a3000
Author: Matt Turner
Date: Thu Apr 2 10:21:16 2015 -0700
nir: Allow abs/neg in select peephole pass.
total instructi
On Fri, Apr 17, 2015 at 2:05 PM, Matt Turner wrote:
> On Fri, Apr 17, 2015 at 2:02 PM, Jason Ekstrand wrote:
>> What made the difference here?
>
> I think it's probably just that
>
> commit 4dacb212fdcc82def02b8c9233f94caa5a8a3000
> Author: Matt Turner
> Date: Thu Apr 2 10:21:16 2015 -0700
>
>
I missed the fact that the ARB_fragment_program SWZ instruction allows
per-component negation. To fix this, move Abs/Negate handling into both
the simple case and the SWZ case's per-component loop.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=9
Signed-off-by: Kenneth Graunke
---
s
On Fri, Apr 17, 2015 at 2:32 PM, Kenneth Graunke wrote:
> I missed the fact that the ARB_fragment_program SWZ instruction allows
> per-component negation. To fix this, move Abs/Negate handling into both
> the simple case and the SWZ case's per-component loop.
>
> Bugzilla: https://bugs.freedeskto
Ping.
On 04/16/2015 03:52 PM, Brian Paul wrote:
This should be more efficient than the previous snprintf() solution.
But more importantly, it avoids a buffer overflow bug that could result
in crashes or unpredictable results when processing very large interface
blocks.
For the app in question,
On 03/03/2015 11:05 AM, Daniel Stone wrote:
Hi,
On 3 March 2015 at 18:56, Jason Ekstrand wrote:
On Tue, Mar 3, 2015 at 10:07 AM, Chad Versace
wrote:
On 02/23/2015 06:32 AM, Jonny Lamb wrote:
+ static const EGLint argb_attrs[] = {
+ EGL_TRANSPARENT_TYPE, EGL_TRANSPARENT_ALPHA_MESA,
+
On 04/17/2015 04:08 PM, James Jones wrote:
On 03/03/2015 11:05 AM, Daniel Stone wrote:
Hi,
On 3 March 2015 at 18:56, Jason Ekstrand wrote:
On Tue, Mar 3, 2015 at 10:07 AM, Chad Versace
wrote:
On 02/23/2015 06:32 AM, Jonny Lamb wrote:
+ static const EGLint argb_attrs[] = {
+ EGL_TRA
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index d7cfe08..20dcc21 100644
--- a/src/mesa/drivers/dri/i965/br
In case of I915_TILING_{X,Y} we need to pass tiling format to libdrm
using drm_intel_bo_alloc_tiled(). But, In case of YF/YS tiled buffers
libdrm need not know about the tiling format because these buffers
don't have hardware support to be tiled or detiled through a fenced
region. libdrm still need
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 80 ++
1 file changed, 80 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 19ff5b8..d7cfe08 100644
--- a/src/mesa/drive
This function will be utilised in later patches.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_context.h| 4
src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat
Reviewed-by: Chris Forbes
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers
Patch continues code refactoring.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 105 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 --
3 files changed,
This series enables skl+ to read/write data to YF/YF tiled
surfaces. A big thanks to Kristian for discussing problems
I faced in writing these patches.
Many piglit tests for texture/buffer data read/write
pass with the new tiling formats. But we still have piglit
regressions in tests using 2D_ARRA
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 68c6634..19f
No other path currently supports uploading data to these surfaces.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_tex_image.c| 24 ++--
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 23 +--
2 files changed, 43 insertions(+), 4 deleti
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index e74e263..68c6634 100644
--- a/src/mesa/d
This will allow Skylake to use _mesa_meta_pbo_GetTexSubImage() for reading YF/YS
tiled surfaces.
V2: Make changes suggested by Neil.
Signed-off-by: Anuj Phogat
Cc: Neil Roberts
---
src/mesa/drivers/common/meta.h | 1 +
src/mesa/drivers/common/meta_tex_subimage.c | 43 ++
This patch sets the tiled resource mode for texture and renderbuffer
surfaces.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_defines.h| 6 ++
src/mesa/drivers/dri/i965/gen8_surface_state.c | 22 ++
2 files changed, 28 insertions(+)
diff --git a/sr
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 10 +-
src/mesa/drivers/dri/i965/intel_tex_image.c | 7 ---
2 files changed, 1 insertion(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pi
This refactoring is required by later patches in this series.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 19 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 31 ++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 19 +++
and some more code refactoring. No functional changes in this patch.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 89 --
1 file changed, 48 insertions(+), 41 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/me
Conditions modified allow skl+ to use blitter:
- for all tiling formats
- to write data to YF/YS tiled surfaces
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i96
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 74 ++
1 file changed, 74 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 20dcc21..9342101 100644
--- a/src/mesa/drive
This fixed the buffer corruption happening in a FBO which use YF/YS
tiled renderbuffer or texture as color attachment.
Spec recommends disabling mip tails for non-mip-mapped surfaces.
But, with this enabled I couldn't get correct data out of YF/YS
tiled surface. I get the expected data with this d
Note: Yf/Ys tiling stays disabled to avoid any piglit regressions. I'm
working on fixing the remaining piglit failures.
We need to do some benchmarking to come up with conditions to choose
Ys (64 KB) over Yf (4 KB). Any thoughts on how big a texture should
be so that 64 KB tiling is preferred over
Patch sets the alignments for texture and renderbuffer surfaces.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 34 +++---
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mes
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_tex_image.c| 8
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 7 ---
2 files changed, 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 8
This patch enables using XY_FAST_COPY_BLT only for Yf/Ys tiled buffers.
Later It can be turned on for other tiling patterns (X,Y).
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_blit.c | 292 +++
src/mesa/drivers/dri/i965/intel_blit.h | 3 +
Currently, that's the only path that supports reading data from these buffers.
Signed-off-by: Anuj Phogat
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 22 --
src/mesa/drivers/dri/i965/intel_tex_image.c | 28
2 files changed, 40 insertions(+
https://bugs.freedesktop.org/show_bug.cgi?id=89960
--- Comment #1 from Vinson Lee ---
Other softpipe piglit regressions:
depthstencil-default_fb-drawpixels-24_8
depthstencil-default_fb-drawpixels-float-and-ushort
draw-pixels
fdo23670-drawpix_stencil
stencil-drawpixels
copy-pixels
fbo-depthsten
On Fri, Mar 13, 2015 at 04:26:28PM +, Neil Roberts wrote:
> The render surface state command for Skylake doesn't have the surface
> array spacing bit so it's not possible to select this layout. I think
> it was only used in order to make it pick a tightly-packed qpitch
> value that doesn't incl
https://bugs.freedesktop.org/show_bug.cgi?id=90081
Bug ID: 90081
Summary: [llvmpipe] piglit
ext_transform_feedback-immediate-reuse-uniform-buffer
regression
Product: Mesa
Version: git
Hardware: x86-64 (A
It wasn't really being used anyway. We used it to assert that gpu_shader5
is supported in the back-end but that should be caught by the front-end.
Signed-off-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
src/
---
src/mesa/drivers/dri/i965/brw_eu.c | 1 +
src/mesa/drivers/dri/i965/brw_eu.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 146202b..e12b890 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/driv
---
src/mesa/drivers/dri/i965/brw_clip.c | 3 +-
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/brw_disasm.c | 162 +++
src/mesa/drivers/dri/i965/brw_eu.c | 8 +-
src/mesa/drivers/dri/i965/brw_eu.h
In future tests, we will start relying on devinfo and not just brw in the
compiler. Changing this now keeps these tests from failing in the future.
---
src/mesa/drivers/dri/i965/test_eu_compact.c| 5 -
src/mesa/drivers/dri/i965/test_fs_cmod_propagation.cpp | 6 +-
src/
---
src/mesa/drivers/dri/i965/brw_eu.c | 2 +-
src/mesa/drivers/dri/i965/brw_eu.h | 12 +-
src/mesa/drivers/dri/i965/brw_eu_compact.c | 198 ++--
src/mesa/drivers/dri/i965/test_eu_compact.c | 4 +-
4 files changed, 107 insertions(+), 109 deletions(-)
This is a series I started working on this week to try and pull as much of
brw_context out of the compiler as possible. With this series, the only
major remaining connections to brw/gl_context are a few trivial things such
as calls to _mesa_problem which should be asserts and shader time.
Why do
---
src/mesa/drivers/dri/i965/brw_context.c | 10 +-
src/mesa/drivers/dri/i965/intel_debug.c | 13 ++---
src/mesa/drivers/dri/i965/intel_debug.h | 4 ++--
src/mesa/drivers/dri/i965/intel_screen.c | 2 ++
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/mesa
---
src/mesa/drivers/dri/i965/brw_clip.c | 2 +-
src/mesa/drivers/dri/i965/brw_clip_line.c| 13 ++---
src/mesa/drivers/dri/i965/brw_clip_tri.c | 4 ++--
src/mesa/drivers/dri/i965/brw_clip_util.c| 12
src/mesa/drivers/dri/i965/brw_eu.c
---
src/mesa/drivers/dri/i965/brw_context.h | 3 ++-
src/mesa/drivers/dri/i965/brw_fs.cpp| 2 +-
src/mesa/drivers/dri/i965/brw_gs.c | 6 --
src/mesa/drivers/dri/i965/brw_vs.c | 8 +---
4 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/b
---
src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
src/mesa/drivers/dri/i965/brw_fs.h| 4 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp| 6 +++---
src/mesa/drivers/dri/i965/brw_vec4.cpp| 6
It's basically just a copy of GEN7_FEATURES only with is_haswell set
---
src/mesa/drivers/dri/i965/brw_device_info.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
index c4350
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 87 +++-
2 files changed, 42 insertions(+), 46 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index a0ee2cc..
---
src/mesa/drivers/dri/i965/brw_context.h| 4 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 54 ++---
src/mesa/drivers/dri/i965/brw_shader.cpp | 13 +
src/mesa/drivers/dri/i965/brw_shader.h | 55 ++
.../drivers/
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 74 ++---
.../drivers/dri/i965/brw_fs_combine_constants.cpp | 10 +-
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_fs_fp.cpp| 4 +-
src/mesa/drivers/dri/i965/brw_fs_nir.cp
---
.../drivers/dri/i965/brw_schedule_instructions.cpp | 21 ++---
src/mesa/drivers/dri/i965/brw_shader.cpp| 4 ++--
src/mesa/drivers/dri/i965/brw_shader.h | 2 +-
3 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965
This name better matches what it's actually used for. The patch was
generated with the following command:
for file in *; do
sed -i -e s/brw_compile/brw_codegen/g $file
done
Signed-off-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_clip.h | 2 +-
src/mesa/drivers/dri/i965/br
This also involves moving revision checking to screen creation time and
passing that into brw_get_device_info so that we can get the right
device_info for early versions of SKL. Since the only place we used
revision was to check for SIMD16 3-src instruction support, it's safe to
remove the revisio
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 5 +++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 5 +++--
src/mesa/drivers/dri/i965/intel_asm_annotation.c | 9 +
src/mesa/drivers/dri/i965/intel_asm_annotation.h | 5 +++--
4 files changed, 14 insertions(+), 10 deletions(-)
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 116 -
2 files changed, 58 insertions(+), 59 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index fa2a028..6dba3
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 ++-
src/mesa/drivers/dri/i965/brw_shader.cpp | 13 +
src/mesa/drivers/dri/i965/brw_shader.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 11 ++-
4 files changed, 27 insertions(+)
---
src/mesa/drivers/dri/i965/brw_fs.h | 1 -
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 11 +--
2 files changed, 1 insertion(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 32063f0..fa2a028 100644
--- a/sr
Since commit 2881b123, we have used 0/~0 for representing booleans on all
gens. However, we still had a bunch of places in the visitor code where we
were still referring to ctx->Const.UniformBooleanTrue. Since this is
always ~0, we can just remove them.
Reviewed-by: Kenneth Graunke
---
src/mes
This creates the options at screen cration time and then we just copy them
into the context at context creation time. We also move is_scalar to the
brw_compiler structure.
We also end up manually setting some values that the core would have set by
default for us. Fortunately, there are only two
https://bugs.freedesktop.org/show_bug.cgi?id=90081
--- Comment #1 from Roland Scheidegger ---
Ah yes I actually knew about that but didn't consider it all that important.
The reason is that the code was already buggy and this change just exposed the
bug.
In short here's what happens:
- the trans
Hi,
when looking at a regression (piglit
ext_transform_feedback-immediate-reuse-uniform-buffer, bug 90081) I
realized that behavior wrt non-size-aligned constant buffers doesn't
seem to be all that clear cut. In particular I'm wondering if what the
test (or rather the state tracker) does is actual
1 - 100 of 103 matches
Mail list logo
