Signed-off-by: Kenneth Graunke
Cc: "10.2"
---
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index 6951f88..db66d68 100
I don't see any reason for this to exist.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index c56f479..c63
Broadwell requires the number of vertices written by the geometry shader
to be specified in a separate register, as part of the terminating
message's payload.
This also means GS_OPCODE_THREAD_END needs to increment mlen.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_vec4_gene
Either should work.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index bf904c6
We're going to add a Gen8+ case shortly, which would need to duplicate
this code again. Instead, share it.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 28
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drive
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 14 --
src/mesa/drivers/dri/i965/brw_vec4.cpp| 12 +++-
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 12 +++-
3 files changed, 10 insertions(+), 28 deletions(-)
d
According to the documentation, we need to set the source 0 register
type to IMM for flow control instructinos that have both JIP and UIP.
Out of paranoia, just make all flow control instructions use IMM;
there's no benefit to using ARF anyway, and it could trouble that's
difficult to diagnose.
Se
Kind of a moot point since we're deleting Gen8 code generation, but
this at least helps make it match the Gen4-7 code. It's probably more
reasonable than using float.
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 6 --
src/mesa/drivers/dri/i965/gen8_
On Haswell, we implement "discard" via predicated SEND messages, using
f0.1 instead of f0.0. To accomplish this, we set inst->flag_subreg to 1
on the FS_OPCODE_FB_WRITE.
Most instructions using fs_inst::flag_subreg expand to a single assembly
instruction. However, FS_OPCODE_FB_WRITE can generate
When we combine the Gen4-7 and Gen8+ generators, we'll need to handle
half float packing/unpacking functions somehow. The Gen8+ generator
code today just emulates the behavior of the Gen7 F32TO16/F16TO32
instructions, including the align16 mode bugs.
Rather than messing with fs_generator/vec4_gen
Everything should be in place to unify code generation between Gen4-7
and Gen8+. We should be able to drop the Gen8 generators at this point.
However, leave them hooked up for a brief moment, for testing and
comparison purposes. Set GEN8=1 to use the old Gen8+ code generator
paths.
Signed-off-b
g0.5 has nothing of value to contribute to m0.5. In both the VS and GS
payload, g0.5 contains the scratch space pointer - which is definitely
not of any use. The GS payload also contains FFTID, but the URB write
message header doesn't want FFTID.
The only reason I used OR was because Eric origin
Signed-off-by: Kenneth Graunke
Cc: "10.2"
---
src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index db66d68..bf904c6 100644
--- a/src/mesa/
Hello,
This series finishes getting Broadwell to use brw_eu_emit.c, and finally
kills off gen8_*_generator.* and gen8_instruction.*. The diffstat is
quite encouraging:
16 files changed, 147 insertions(+), 4152 deletions(-)
While doing this work, I've been diffing the assembly generated via b
This improves performance in Trine 2 at 1280x720 (windowed) on "Very
High" settings by 30% (in the interactive menu) to 45% (in the forest
by the giant frog) on Haswell GT3e.
It also now generates the same assembly on Gen7 as it does on Gen8,
which always used the sampler for both types.
Signed-o
On Mon, Aug 11, 2014 at 07:53:11PM -0700, Ben Widawsky wrote:
> On Mon, Aug 11, 2014 at 05:29:31PM -0700, Kristian Høgsberg wrote:
> > Right now we decide which kernels to use and the GRF start offsets in
> > one place and emit the kernel pointers later. The logic of how to map
> > 8, 16 and 32 ke
On Monday, August 11, 2014 11:22:22 AM Matt Turner wrote:
> Comparing ~0u with a packed enum (i.e., 1 byte) always evaluates to
> false. Shouldn't gcc warn about this?
>
> Reported-by: Connor Abbott
Looks good to me.
Reviewed-by: Kenneth Graunke
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Description: This is a digitally
On Mon, Aug 11, 2014 at 08:08:33PM -0700, Ben Widawsky wrote:
> On Mon, Aug 11, 2014 at 05:29:32PM -0700, Kristian Høgsberg wrote:
> > For now, this can only be triggered with a new 'no8' INTEL_DEBUG option
> > and a new context flag. We'll use the context flag later, but introducing
> > it now le
On Monday, August 11, 2014 07:53:11 PM Ben Widawsky wrote:
> On Mon, Aug 11, 2014 at 05:29:31PM -0700, Kristian Høgsberg wrote:
[snip]
> > diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > b/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > index 3d6d7f0..f58d49c 100644
> > --- a/src/mesa/dri
On Mon, Aug 11, 2014 at 08:21:29PM -0700, Ben Widawsky wrote:
> On Mon, Aug 11, 2014 at 05:29:34PM -0700, Kristian Høgsberg wrote:
> > The brw_draw_prims() function is the draw entry point into the driver,
> > and takes struct _mesa_prim for input. We want to be able to feed
> > native primitives
On Mon, Aug 11, 2014 at 08:46:23PM -0400, Ilia Mirkin wrote:
> On Mon, Aug 11, 2014 at 8:29 PM, Kristian Høgsberg wrote:
> > diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c
> > b/src/mesa/drivers/dri/i965/intel_tex_copy.c
> > index 97f1569..2456080 100644
> > --- a/src/mesa/drivers/dri/i9
On Monday, August 11, 2014 05:29:31 PM Kristian Høgsberg wrote:
> Right now we decide which kernels to use and the GRF start offsets in
> one place and emit the kernel pointers later. The logic of how to map
> 8, 16 and 32 kernels to kernel start pointers follows the same logic as which
> GRF star
On Monday, August 11, 2014 05:29:38 PM Kristian Høgsberg wrote:
> This matches the name of the dd hook. Also convert a couple of nearby
> dd implementations to lowercase + underscore as is now the standard.
>
> Signed-off-by: Kristian Høgsberg
> ---
> src/mesa/drivers/dri/i965/brw_context.c | 1
On Mon, Aug 11, 2014 at 10:48:49PM -0700, Kenneth Graunke wrote:
> On Monday, August 11, 2014 05:29:31 PM Kristian Høgsberg wrote:
> > Right now we decide which kernels to use and the GRF start offsets in
> > one place and emit the kernel pointers later. The logic of how to map
> > 8, 16 and 32 ke
On Mon, Aug 11, 2014 at 10:40:25PM -0700, Kenneth Graunke wrote:
> On Monday, August 11, 2014 07:53:11 PM Ben Widawsky wrote:
> > On Mon, Aug 11, 2014 at 05:29:31PM -0700, Kristian Høgsberg wrote:
> [snip]
> > > diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
> > > b/src/mesa/drivers/dri/i9
On Mon, Aug 11, 2014 at 11:18:36PM -0700, Ben Widawsky wrote:
> On Mon, Aug 11, 2014 at 10:40:25PM -0700, Kenneth Graunke wrote:
> > On Monday, August 11, 2014 07:53:11 PM Ben Widawsky wrote:
> > > On Mon, Aug 11, 2014 at 05:29:31PM -0700, Kristian Høgsberg wrote:
> > [snip]
> > > > diff --git a/sr
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