2011/9/2 Chia-I Wu :
> On Thu, Sep 1, 2011 at 5:53 PM, Benjamin Franzke
> wrote:
>> In preparation for wayland ALPHA_FORMAT usage,
>> see commit 7b1d94e5d1f53ac5f59000176aea1d02fc9a1181.
>>
>> Changes:
>> - New native_config surface_type bit: alpha_format_pre_bit
>> - Introduction of native_surf
Am Donnerstag, den 01.09.2011, 19:54 +0100 schrieb Andy Furniss:
> Christian König wrote:
>
> > Looks like there is some garbage at the end of the stream, mplayer is
> > also complaining nicely about "TS_PARSE: COULDN'T SYNC".
>
> I played around a bit more, it seems that rather than garbage it's
Christian König wrote:
MPlayer 1.0rc4-4.5.2 works flawless with the snooker-short.ts video. So
it is definitely some difference between this version and svn version.
I agree - 1.0rc4 (4.2.3) also works for me.
The difference between sound/-nosound is probably just some different
memory alloc
https://bugs.freedesktop.org/show_bug.cgi?id=34401
Thierry Vignaud changed:
What|Removed |Added
CC||thierry.vign...@gmail.com
--
Configur
On Fri, Sep 2, 2011 at 3:27 PM, Benjamin Franzke
wrote:
> 2011/9/2 Chia-I Wu :
>> On Thu, Sep 1, 2011 at 5:53 PM, Benjamin Franzke
>> wrote:
>>> In preparation for wayland ALPHA_FORMAT usage,
>>> see commit 7b1d94e5d1f53ac5f59000176aea1d02fc9a1181.
>>>
>>> Changes:
>>> - New native_config surfac
The preferred solution to keeping track of the picture structure
has been putting it in the state tracker, so use picture_structure
instead of frame_started to check if a frame needs to begin.
If picture_structure has been changed, end the frame and start again.
Signed-off-by: Maarten Lankhorst
From: Eugeni Dodonov
This could happen in 3 different cases, and ERRNO can explain what
happened. First case would be EIO (gpu hang), second EINVAL (something is
wrong inside the batch), and we also discovered that sometimes it happens
with ENOSPACE. All of those cases are different it it could b
This patch series modifies the i965 driver code that relates to
the layout of vertex attributes in the VUE (vertex URB entry).
Previously the layout of vertex attributes was implicit in a
large number of different source files, and was not always
consistent (for instance, some code forgot to accoun
Previously, this conversion was duplicated in several places in the
i965 driver. This patch moves it to a common location in mtypes.h,
near the declaration of gl_vert_result and gl_frag_attrib.
I've also added comments to remind us that we may need to revisit the
conversion code when adding eleme
Several places in the i965 code make implicit assumptions about the
structure of data in the VUE (vertex URB entry). This patch adds a
function, brw_compute_vue_map(), which computes the structure of the
VUE explicitly. Future patches will modify the rest of the driver to
use the explicitly compu
Some parts of the i965 driver keep track of locations within the VUE
(vertex URB entry) using byte offsets. This patch adds inline
functions to compute these byte offsets using the VUE map.
---
src/mesa/drivers/dri/i965/brw_context.h | 18 ++
1 files changed, 18 insertions(+), 0
---
src/mesa/drivers/dri/i965/brw_vs.h |2 +-
src/mesa/drivers/dri/i965/brw_vs_emit.c | 179 ---
2 files changed, 69 insertions(+), 112 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h
b/src/mesa/drivers/dri/i965/brw_vs.h
index beccb38..a02c06d 1
Previously, the old VS backend computed the URB entry size by adding
the number of vertex shader outputs to the size of the URB header.
This often produced a larger result than necessary, because some
vertex shader outputs are stored in the header, so they were being
double counted. This patch cha
Previously, emit_vue_header_gen4() used local variables to keep track
of which registers were storing the NDC and HPOS. This patch uses the
output_reg[] array instead, so that the code that manipulates NDC and
HPOS can be more easily refactored.
---
src/mesa/drivers/dri/i965/brw_vec4.h
---
src/mesa/drivers/dri/i965/brw_vec4.h |1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index dfe9c02..9b93296 100644
-
---
src/mesa/drivers/dri/i965/brw_vec4.h |1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 39 +--
2 files changed, 23 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 9b93296..8
---
src/mesa/drivers/dri/i965/brw_vec4.h |1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 32 ++-
2 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 8c613bd..0
Previously, the new VS backend used two functions,
emit_vue_header_gen6() and emit_vue_header_gen4() to emit the fixed
parts of the VUE, and then a pair of carefully-constructed loops to
emit the rest of the VUE, leaving out the parts that were already
emitted as part of the header.
This patch cha
max_usable_mrf has been carefully set such that (max_usable_mrf -
base_mrf) is a multiple of 2, so that an even number of VUE slots are
emitted with each URB write (which Gen6 requires). This patch adds an
assertion to confirm that this is the case, and moves the comment to
this effect to be near
Previously, the new VS backend computed the size of the URB entry by
counting the number of MRFs used in emitting the URB entry. Now it
just gets it straight from the VUE map.
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |9 ++---
1 files changed, 2 insertions(+), 7 deletions(-)
di
This patch moves the computation of the SF URB entry read offset from
upload_sf_unit() to its own function, so that it can be re-used when
creating the gen4-5 SF program.
---
src/mesa/drivers/dri/i965/brw_sf.h |1 +
src/mesa/drivers/dri/i965/brw_sf_state.c | 20
2
---
src/mesa/drivers/dri/i965/brw_sf.c |8 ++-
src/mesa/drivers/dri/i965/brw_sf.h |5 +++-
src/mesa/drivers/dri/i965/brw_sf_emit.c | 32 --
3 files changed, 32 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c
b/src
The new function, called get_vert_result(), uses the VUE map to find
the register containing a given vertex attribute. Previously, we used
the attr_to_idx[] array, which served the same purpose but didn't
account for gl_PointSize correctly.
This fixes a bug on pre-Gen6 wherein the back side of a
Previously, some of the code in SF erroneously used bitfields based on
the gl_frag_attrib enum when actually referring to vertex results.
This worked, because coincidentally the particular enum values being
used happened to match between gl_frag_attrib and gl_vert_result. But
it was fragile, becau
Previously, SF code used the idx_to_attr[] array to compute the
location of entries in the VUE map. This array didn't properly
account for gl_PointSize. Now we use the VUE map directly.
---
src/mesa/drivers/dri/i965/brw_sf_emit.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
These data structures were serving the same purpose as the VUE map,
but were buggy. Now that the code has been transitioned to use the
VUE map, they are not needed.
---
src/mesa/drivers/dri/i965/brw_sf.c | 12 +---
src/mesa/drivers/dri/i965/brw_sf.h |2 --
2 files changed, 1 inserti
Previously, the SF used nr_setup_attrs to determine whether it was
looking at the last element of the VUE. Changed this code to use the
VUE map.
---
src/mesa/drivers/dri/i965/brw_sf_emit.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sf_e
This patch removes the variables nr_attrs and nr_setup_attrs, whose
purpose is now being served by the VUE map. nr_attr_regs and
nr_setup_regs are still needed, however they are now computed using
the VUE map rather than by counting the number of vertex shader
outputs (which caused subtle bugs whe
This patch changes get_attr_override() (which computes the
relationship between vertex shader outputs and fragment shader inputs)
to use the VUE map.
---
src/mesa/drivers/dri/i965/brw_state.h |3 +-
src/mesa/drivers/dri/i965/gen6_sf_state.c | 108 +
src/mesa/dr
---
src/mesa/drivers/dri/i965/gen6_sf_state.c |5 +++--
src/mesa/drivers/dri/i965/gen7_sf_state.c |5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 5e121f7..713a4eb 100644
--
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 16
src/mesa/drivers/dri/i965/gen7_sf_state.c | 16
2 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 713
---
src/mesa/drivers/dri/i965/brw_clip.c |3 +++
src/mesa/drivers/dri/i965/brw_clip.h |5 -
2 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c
b/src/mesa/drivers/dri/i965/brw_clip.c
index b49c9f4..b9ec55a 100644
--- a/src/mesa/drivers/d
---
src/mesa/drivers/dri/i965/brw_clip.c |2 +-
src/mesa/drivers/dri/i965/brw_clip.h |2 +-
src/mesa/drivers/dri/i965/brw_clip_unfilled.c |2 +-
src/mesa/drivers/dri/i965/brw_clip_util.c |2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src
The offsets within the VUE of HPOS and NDC are needed only in a few
auxiliary clipping functions. This patch moves computation of those
offsets into the functions that need them, and does the computation
using the VUE map.
---
src/mesa/drivers/dri/i965/brw_clip.c |2 --
src/mesa/driv
---
src/mesa/drivers/dri/i965/brw_clip_tri.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_tri.c
b/src/mesa/drivers/dri/i965/brw_clip_tri.c
index 0f938fe..359f76f 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_tri.c
+++ b/src/mes
This makes header_regs available for computing VUE offsets within clip code.
---
src/mesa/drivers/dri/i965/brw_clip.c |9 -
src/mesa/drivers/dri/i965/brw_clip.h |1 +
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c
b/src/mesa/dri
---
src/mesa/drivers/dri/i965/brw_clip_util.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 8cbb2ff..0342aa5 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/m
---
src/mesa/drivers/dri/i965/brw_clip_util.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index 0342aa5..e90f146 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b
Previously we would examine the offset[] array (since an offset of 0
meant "not in use"). This paves the way for removing the offset[]
array.
---
src/mesa/drivers/dri/i965/brw_clip.h |9 +
src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 14 +-
src/mesa/drivers/d
This patch replaces some ad-hoc computations using ATTR_SIZE and the
offset[] array to use the VUE map functions
brw_vert_result_to_offset() and brw_vue_slot_to_offset().
---
src/mesa/drivers/dri/i965/brw_clip_tri.c |2 +-
src/mesa/drivers/dri/i965/brw_clip_unfilled.c | 32 +
---
src/mesa/drivers/dri/i965/brw_clip.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.c
b/src/mesa/drivers/dri/i965/brw_clip.c
index f33518b..8929160 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dr
Previously, brw_clip_interp_vertex() iterated only through the
"non-header" elements of the VUE when performing interpolation
(because header elements don't need interpolation). This code now
refers exclusively to the VUE map to figure out which elements need
interpolation, so that brw_clip_interp
The variables offset[], idx_to_attr[], nr_bytes, nr_attrs, and
header_regs were all serving purposes which are now served by the VUE
map.
---
src/mesa/drivers/dri/i965/brw_clip.c | 23 ---
src/mesa/drivers/dri/i965/brw_clip.h | 11 +--
2 files changed, 1 insertions(
The previous computation had two bugs: (a) it used a formula based on
Gen5 for Gen6 and Gen7 as well. (b) it failed to account for the fact
that PSIZ is stored in the VUE header. Fortunately, both bugs caused
it to compute a URB size that was too large, which was benign. This
patch computes the U
They are needed by glsl_to_tgsi for an efficient implementation using native
integers.
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 30
src/gallium/auxiliary/tgsi/tgsi_info.c |3 ++
src/gallium/include/pipe/p_shader_tokens.h |5 +++-
3 files changed,
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 18 +++---
1 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index e2857ed..05d4d33 100644
--- a/src/mesa/state_tracker/st_glsl_to_t
On Fri, Sep 02, 2011 at 06:15:00PM +0200, Maarten Lankhorst wrote:
> Try to use the PMPEG where available
>
> Signed-off-by: Maarten Lankhorst
>
> ---
> diff --git a/src/gallium/drivers/nouveau/nouveau_video.c
> b/src/gallium/drivers/nouveau/nouveau_video.c
> index 620c030..2b90056 100644
> ---
Hi,
While debugging some code I ran across the following situation:
- pipe_context c1 is created
- pipe_surface s1 is created
- strb-> surface is set to s1 (s1's refcount goes up)
- pipe_context c1 is destroyed
- strb is destroyed
- strb->surface is destroyed (so s1's refcount is now 0 and we wan
This differs from the FS in that we track constants in each
destination channel, and we we have to look at all the swizzled source
channels. Also, the instruction stream walk is done in an O(n) manner
instead of O(n^2).
Across shader-db, this reduces 8.0% of the instructions from 60.0% of
the ver
Further reduces instruction count by 4.0% in 40.7% of the vertex
shaders.
---
.../drivers/dri/i965/brw_vec4_copy_propagation.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_v
This only occurs for GRFs, and hasn't mattered until now because we
only copy propagated non-GRFs.
---
.../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 15 ---
1 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
Removes 2.0% of the instructions from 35.7% of vertex shaders in shader-db.
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +
src/mesa/drivers/dri/i965/brw_vec4.h |2 +
.../drivers/dri/i965/brw_vec4_copy_propagation.cpp | 58 +++-
3 files chan
On Fri, 2 Sep 2011 11:58:45 +0800, Chia-I Wu wrote:
> On Fri, Sep 2, 2011 at 4:09 AM, Eric Anholt wrote:
> > On Wed, 31 Aug 2011 13:46:35 +0800, Chia-I Wu wrote:
> >> From: Chia-I Wu
> >>
> >> Surfaces of the format can only be sampled from but not render to.
> >
> > Does the usage of this form
- Original Message -
> Hi,
>
> While debugging some code I ran across the following situation:
>
> - pipe_context c1 is created
> - pipe_surface s1 is created
> - strb-> surface is set to s1 (s1's refcount goes up)
> - pipe_context c1 is destroyed
> - strb is destroyed
> - strb->surface i
On Fri, 2 Sep 2011 12:33:44 -0300, Eugeni Dodonov wrote:
> From: Eugeni Dodonov
>
> This could happen in 3 different cases, and ERRNO can explain what
> happened. First case would be EIO (gpu hang), second EINVAL (something is
> wrong inside the batch), and we also discovered that sometimes it
On Fri, 2 Sep 2011 09:06:40 -0700, Paul Berry wrote:
> Previously, this conversion was duplicated in several places in the
> i965 driver. This patch moves it to a common location in mtypes.h,
> near the declaration of gl_vert_result and gl_frag_attrib.
>
> I've also added comments to remind us
On Fri, Sep 2, 2011 at 15:53, Eric Anholt wrote:
> On Fri, 2 Sep 2011 12:33:44 -0300, Eugeni Dodonov
> wrote:
> > From: Eugeni Dodonov
> >
> > This could happen in 3 different cases, and ERRNO can explain what
> > happened. First case would be EIO (gpu hang), second EINVAL (something is
> > wr
On Fri, 2 Sep 2011 09:06:41 -0700, Paul Berry wrote:
> Several places in the i965 code make implicit assumptions about the
> structure of data in the VUE (vertex URB entry). This patch adds a
> function, brw_compute_vue_map(), which computes the structure of the
> VUE explicitly. Future patches
On Fri, 2 Sep 2011 09:06:44 -0700, Paul Berry wrote:
> Previously, the old VS backend computed the URB entry size by adding
> the number of vertex shader outputs to the size of the URB header.
> This often produced a larger result than necessary, because some
> vertex shader outputs are stored in
On Fri, 2 Sep 2011 09:06:48 -0700, Paul Berry wrote:
> ---
> src/mesa/drivers/dri/i965/brw_vec4.h |1 +
> src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 32 ++-
> 2 files changed, 20 insertions(+), 13 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/
On Fri, 2 Sep 2011 09:07:00 -0700, Paul Berry wrote:
> This patch changes get_attr_override() (which computes the
> relationship between vertex shader outputs and fragment shader inputs)
> to use the VUE map.
> ---
> src/mesa/drivers/dri/i965/brw_state.h |3 +-
> src/mesa/drivers/dri/i96
On Fri, 2 Sep 2011 09:07:10 -0700, Paul Berry wrote:
> Previously we would examine the offset[] array (since an offset of 0
> meant "not in use"). This paves the way for removing the offset[]
> array.
> ---
> src/mesa/drivers/dri/i965/brw_clip.h |9 +
> src/mesa/drivers/dri
On Fri, 2 Sep 2011 09:07:11 -0700, Paul Berry wrote:
> This patch replaces some ad-hoc computations using ATTR_SIZE and the
> offset[] array to use the VUE map functions
> brw_vert_result_to_offset() and brw_vue_slot_to_offset().
> ---
> src/mesa/drivers/dri/i965/brw_clip_tri.c |2 +-
>
On Fri, 2 Sep 2011 09:06:39 -0700, Paul Berry wrote:
> This patch series modifies the i965 driver code that relates to
> the layout of vertex attributes in the VUE (vertex URB entry).
> Previously the layout of vertex attributes was implicit in a
> large number of different source files, and was
On 2 September 2011 14:48, Eric Anholt wrote:
> On Fri, 2 Sep 2011 09:06:39 -0700, Paul Berry
> wrote:
> > This patch series modifies the i965 driver code that relates to
> > the layout of vertex attributes in the VUE (vertex URB entry).
> > Previously the layout of vertex attributes was implic
On 2 September 2011 11:59, Eric Anholt wrote:
> On Fri, 2 Sep 2011 09:06:40 -0700, Paul Berry
> wrote:
> > Previously, this conversion was duplicated in several places in the
> > i965 driver. This patch moves it to a common location in mtypes.h,
> > near the declaration of gl_vert_result and g
On 2 September 2011 12:47, Eric Anholt wrote:
> On Fri, 2 Sep 2011 09:06:41 -0700, Paul Berry
> wrote:
> > Several places in the i965 code make implicit assumptions about the
> > structure of data in the VUE (vertex URB entry). This patch adds a
> > function, brw_compute_vue_map(), which compu
Are there any objections to pushing this?
Bryan
On 08/31/2011 01:33 AM, Bryan Cain wrote:
> With this patch, there are no piglit regressions on softpipe with native
> integers enabled. Unlike my previous patch, this uses integer values of
> ~0 and 0 for true and false, respectively, instead of t
On 2 September 2011 12:59, Eric Anholt wrote:
> On Fri, 2 Sep 2011 09:06:44 -0700, Paul Berry
> wrote:
> > Previously, the old VS backend computed the URB entry size by adding
> > the number of vertex shader outputs to the size of the URB header.
> > This often produced a larger result than nec
On 2 September 2011 13:57, Eric Anholt wrote:
> On Fri, 2 Sep 2011 09:07:00 -0700, Paul Berry
> wrote:
> > This patch changes get_attr_override() (which computes the
> > relationship between vertex shader outputs and fragment shader inputs)
> > to use the VUE map.
> > ---
> > src/mesa/drivers/
On 2 September 2011 14:40, Eric Anholt wrote:
> On Fri, 2 Sep 2011 09:07:10 -0700, Paul Berry
> wrote:
> > Previously we would examine the offset[] array (since an offset of 0
> > meant "not in use"). This paves the way for removing the offset[]
> > array.
> > ---
> > src/mesa/drivers/dri/i96
On Wed, 31 Aug 2011 01:33:59 -0500, Bryan Cain wrote:
> With this patch, there are no piglit regressions on softpipe with native
> integers enabled. Unlike my previous patch, this uses integer values of
> ~0 and 0 for true and false, respectively, instead of the float values 1.0
> and 0.0.
This
2011/9/2 Jose Fonseca :
> - Original Message -
>> Hi,
>>
>> While debugging some code I ran across the following situation:
>>
>> - pipe_context c1 is created
>> - pipe_surface s1 is created
>> - strb-> surface is set to s1 (s1's refcount goes up)
>> - pipe_context c1 is destroyed
>> - strb
2011/9/2 Stéphane Marchesin :
> 2011/9/2 Jose Fonseca :
>> - Original Message -
>>> Hi,
>>>
>>> While debugging some code I ran across the following situation:
>>>
>>> - pipe_context c1 is created
>>> - pipe_surface s1 is created
>>> - strb-> surface is set to s1 (s1's refcount goes up)
>>>
On 09/02/2011 06:13 PM, Eric Anholt wrote:
> On Wed, 31 Aug 2011 01:33:59 -0500, Bryan Cain wrote:
>> With this patch, there are no piglit regressions on softpipe with native
>> integers enabled. Unlike my previous patch, this uses integer values of
>> ~0 and 0 for true and false, respectively, i
2011/9/2 Stéphane Marchesin :
> 2011/9/2 Jose Fonseca :
>> - Original Message -
>>> Hi,
>>>
>>> While debugging some code I ran across the following situation:
>>>
>>> - pipe_context c1 is created
>>> - pipe_surface s1 is created
>>> - strb-> surface is set to s1 (s1's refcount goes up)
>>>
Whoops, forgot to copy the list on this reply.
-- Forwarded message --
From: Paul Berry
Date: 2 September 2011 15:46
Subject: Re: [PATCH 09/36] i965: new VS: move clip distance computation
(GEN5+) to a separate function.
To: Eric Anholt
On 2 September 2011 13:13, Eric Anholt w
On 2 September 2011 15:46, Paul Berry wrote:
> On 2 September 2011 13:13, Eric Anholt wrote:
>
>> On Fri, 2 Sep 2011 09:06:48 -0700, Paul Berry
>> wrote:
>> > ---
>> > src/mesa/drivers/dri/i965/brw_vec4.h |1 +
>> > src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 32
>> ++
When we tried to retype a brw_null_reg() in CMP(), the retyping didn't
take effect because HW_REG just ignores the type field.
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.
This series gets gen4 to be non-regressing for the new vertex shader.
I'd be fine with not pushing the last patch and letting Paul's patches
land, then fixing the bug as it remains there. Once these two land, I
think it's time to turn on the new backend by default.
___
If you get your total GRF count wrong, you write over some other
shader's g0, and the GPU fails shortly thereafter.
---
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
Fixes vs-pow-float-float and friends.
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |5 -
1 files changed, 0 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 2d1c878..4b8b276 100644
--- a/src/mesa
On the old backend, we used scalar mode because Mesa IR math is
result.xyzw = math(op0.), which matched up well. However, in GLSL
IR we do things like result.xy = math(op0.xy), so we want vector mode.
For the common case of result.x = math(op0.x), performance will be the
same (no cost for un-e
This is required to ensure ordering between reads and writes within a
thread.
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 24 ++--
1 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/br
Fixes a giant pile of VS tests on gen4.
---
src/mesa/drivers/dri/i965/brw_vec4.h |4 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 50 +++-
2 files changed, 33 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/dr
We were passing an MRF as the source argument, instead of using the
implied move and putting the MRF number in the proper place in the
instruction encoding.
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp | 32 +++---
1 files changed, 14 insertions(+), 18 deletions(-)
diff -
The second vertex was getting a garbage index.
---
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 828a9c1..61a1092 100644
--- a/sr
Fixes glsl-vs-point-size.
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 22f8763..f33442b 100644
--- a/src/me
We were failing to relocate, so on the first draw run our scratch
would tend to get written to 0x0.
---
src/mesa/drivers/dri/i965/brw_vs_state.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c
b/src/mesa/drivers/dri/i965/
On Fri, 2 Sep 2011 17:40:39 -0700, Paul Berry wrote:
Non-text part: multipart/alternative
> On 2 September 2011 15:46, Paul Berry wrote:
>
> > On 2 September 2011 13:13, Eric Anholt wrote:
> >
> >> On Fri, 2 Sep 2011 09:06:48 -0700, Paul Berry
> >> wrote:
> >> > ---
> >> > src/mesa/drivers/d
On 2 September 2011 18:37, Eric Anholt wrote:
> This series gets gen4 to be non-regressing for the new vertex shader.
> I'd be fine with not pushing the last patch and letting Paul's patches
> land, then fixing the bug as it remains there. Once these two land, I
> think it's time to turn on the
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