I did today run these patches against piglit glsl tests and there was
no regressions. I did go testing write the attached patch on top of
this set, it change MULs with explicit accumulator write into implicit
accumulator write. I guess what Eric said mean something like the
attached patch is needed
Hi Matt,
the changed set looks good to me, I did side by side comparison on
what had changed but did not try to run it today. I realized
immediately when seeing your comment I had not understood to consider
the "WAR" vs. "RAW" comments in the scheduler. I was thinking when I
made the latest set th
On Fri, Apr 4, 2014 at 6:51 AM, Juha-Pekka Heikkila
wrote:
> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> index a951459..92f82fd 100644
> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> +++ b/src
On Fri, Mar 28, 2014 at 6:28 AM, Juha-Pekka Heikkila
wrote:
> + if (inst->writes_accumulator||inst->writes_flag())
Spaces around ||
> inst->dst = dst_reg(retype(brw_null_reg(), inst->dst.type));
> - break;
> - default:
> - if (inst->writes_flag()) {
> -
On Fri, Mar 28, 2014 at 6:28 AM, Juha-Pekka Heikkila
wrote:
> diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> index a951459..492ee0d 100644
> --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
> +++ b/sr
