Re: [Mesa-dev] [RFC v2 12/15] i965: correct VALIGN for 2d textures on Skylake

2015-06-09 Thread Ian Romanick
On 06/01/2015 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > In agreement with commit 4ab8d59a23, vertical alignment values are equal to > four times the block height on Gen9+. > > Signed-off-by: Nanley Chery > --- > src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +-- > 1 file chan

Re: [Mesa-dev] [RFC v2 12/15] i965: correct VALIGN for 2d textures on Skylake

2015-06-02 Thread Neil Roberts
Actually, having said that I think it would make more sense to change the line to: return brw->gen >= 9 ? j * 4 : j; The 4 that it was returning for Gen<9 is supposed to represent the block height and I don't think there's any reason to hard-code it seeing as we are now querying the block h

Re: [Mesa-dev] [RFC v2 12/15] i965: correct VALIGN for 2d textures on Skylake

2015-06-01 Thread Neil Roberts
Looks good to me. Reviewed-by: Neil Roberts - Neil Anuj Phogat writes: > Adding Neil to Cc who committed 4ab8d59. > > Reviewed-by: Anuj Phogat ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/me

Re: [Mesa-dev] [RFC v2 12/15] i965: correct VALIGN for 2d textures on Skylake

2015-06-01 Thread Anuj Phogat
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery wrote: > From: Nanley Chery > > In agreement with commit 4ab8d59a23, vertical alignment values are equal to > four times the block height on Gen9+. > > Signed-off-by: Nanley Chery > --- > src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +-- > 1 f

[Mesa-dev] [RFC v2 12/15] i965: correct VALIGN for 2d textures on Skylake

2015-06-01 Thread Nanley Chery
From: Nanley Chery In agreement with commit 4ab8d59a23, vertical alignment values are equal to four times the block height on Gen9+. Signed-off-by: Nanley Chery --- src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/dr