ssage-
From: Palli, Tapani
Sent: Wednesday, February 14, 2018 9:58 AM
To: Rogovin, Kevin ; Jason Ekstrand
Cc: ML mesa-dev
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
On 14.02.2018 09:54, Tapani Pälli wrote:
>
>
> On 14.02.2018 09:38, Rogovin, Kevi
c:* ML mesa-dev
*Subject:* Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
Random thought:
Nanley and I were talking about this just now and I was complaining
about how much I hate the fact that this workaround exists because we
can't implement it in Vulkan. Then I got an idea. What wou
-Kevin
-Original Message-
From: Palli, Tapani
Sent: Monday, February 12, 2018 10:14 AM
To: Rogovin, Kevin ; Jason Ekstrand
Cc: ML mesa-dev
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
On 02/12/2018 09:44 AM, Tapani Pälli wrote:
Hi;
On 02/08/2018 09:50 AM, Rogo
ly in brw_draw.c for resolving
inputs).
-Kevin
-Original Message-
From: Palli, Tapani
Sent: Monday, February 12, 2018 10:14 AM
To: Rogovin, Kevin ; Jason Ekstrand
Cc: ML mesa-dev
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
On 02/12/2018 09:44 AM, Tapani Pälli wrote:
:* Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
Random thought:
Nanley and I were talking about this just now and I was complaining
about how much I hate the fact that this workaround exists because we
can't implement it in Vulkan. Then I got an idea. What would happen
if we jus
AM
*To:* Rogovin, Kevin
*Cc:* ML mesa-dev
*Subject:* Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
Random thought:
Nanley and I were talking about this just now and I was complaining
about how much I hate the fact that this workaround exists because we
can't implement it in V
.
-Kevin
From: Jason Ekstrand [mailto:ja...@jlekstrand.net]
Sent: Thursday, February 8, 2018 2:47 AM
To: Rogovin, Kevin
Cc: ML mesa-dev
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
Random thought:
Nanley and I were talking about this just now and I was complaining about how
Random thought:
Nanley and I were talking about this just now and I was complaining about
how much I hate the fact that this workaround exists because we can't
implement it in Vulkan. Then I got an idea. What would happen if we just
set MOCS to zero (uncached) for ASTC 5x5 textures? Does that m
;
> -Kevin
>
Hi,
Thanks for giving it a try.
Regards,
Nanley
> -Original Message-
> From: Nanley Chery [mailto:nanleych...@gmail.com]
> Sent: Friday, December 15, 2017 8:34 PM
> To: Rogovin, Kevin
> Cc: mesa-dev@lists.freedesktop.org
> Subject: Re: [Mesa-dev] [PATC
: Friday, December 15, 2017 8:34 PM
To: Rogovin, Kevin
Cc: mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH v2 0/5] i965: ASTC5x5 workaround
On Thu, Dec 14, 2017 at 07:39:46PM +0200, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> This patch series implements a needed w
On Thu, Dec 14, 2017 at 07:39:46PM +0200, kevin.rogo...@intel.com wrote:
> From: Kevin Rogovin
>
> This patch series implements a needed workaround for Gen9 for ASTC5x5
> sampler reads. The crux of the work around is to make sure that the
> sampler does not read an ASTC5x5 texture and a surface w
From: Kevin Rogovin
This patch series implements a needed workaround for Gen9 for ASTC5x5
sampler reads. The crux of the work around is to make sure that the
sampler does not read an ASTC5x5 texture and a surface with an auxilary
buffer without having a texture cache invalidate and command stream
12 matches
Mail list logo
