Re: [Mesa-dev] [PATCH 3/4] radeonsi: disable the TGSI merge registers pass

2017-04-26 Thread Marek Olšák
For patches 1-3: Reviewed-by: Marek Olšák Marek On Tue, Apr 25, 2017 at 12:31 AM, Samuel Pitoiset wrote: > 47109 shaders in 29632 tests > Totals: > SGPRS: 1917364 -> 1916620 (-0.04 %) > VGPRS: 1165802 -> 1165202 (-0.05 %) > Spilled SGPRs: 1880 -> 1843 (-1.97 %) > Spilled VGPRs: 70 -> 65 (-7.14

Re: [Mesa-dev] [PATCH 3/4] radeonsi: disable the TGSI merge registers pass

2017-04-25 Thread Ilia Mirkin
I've hated this pass for quite a while. It is necessary for nv30 but is actively harmful for nv50+ due to the undef issue nha points out. I haven't looked closely at the impl details, but the idea is acked-by me. On Apr 25, 2017 5:44 AM, "Samuel Pitoiset" wrote: > > > On 04/25/2017 08:47 AM, Nic

Re: [Mesa-dev] [PATCH 3/4] radeonsi: disable the TGSI merge registers pass

2017-04-25 Thread Samuel Pitoiset
On 04/25/2017 08:47 AM, Nicolai Hähnle wrote: Interesting find. Is this in shaders with control flow? Perhaps with this change, there are now more undefs in places that previously had a phi with an unrelated use of the same TGSI temporary. Anyway, patches 1-3: Yes. Looks like some shaders ha

Re: [Mesa-dev] [PATCH 3/4] radeonsi: disable the TGSI merge registers pass

2017-04-24 Thread Nicolai Hähnle
Interesting find. Is this in shaders with control flow? Perhaps with this change, there are now more undefs in places that previously had a phi with an unrelated use of the same TGSI temporary. Anyway, patches 1-3: Reviewed-by: Nicolai Hähnle On 25.04.2017 00:31, Samuel Pitoiset wrote: 4710

[Mesa-dev] [PATCH 3/4] radeonsi: disable the TGSI merge registers pass

2017-04-24 Thread Samuel Pitoiset
47109 shaders in 29632 tests Totals: SGPRS: 1917364 -> 1916620 (-0.04 %) VGPRS: 1165802 -> 1165202 (-0.05 %) Spilled SGPRs: 1880 -> 1843 (-1.97 %) Spilled VGPRs: 70 -> 65 (-7.14 %) Private memory VGPRs: 1184 -> 1184 (0.00 %) Scratch size: 1312 -> 1308 (-0.30 %) dwords per thread Code Size: 60211356