Patches 1,2,4:
Reviewed-by: Marek Olšák
I replied on 3 and 6. I'm not sure off hand about 5,7,8.
Marek
On Tue, Nov 10, 2015 at 5:10 AM, Dave Airlie wrote:
> From: Dave Airlie
>
> On some chips the GSVS itemsize needs to be aligned to a cacheline size.
>
> This only applies to some of the r60
From: Dave Airlie
On some chips the GSVS itemsize needs to be aligned to a cacheline size.
This only applies to some of the r600 family chips.
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_state.c | 20
1 file changed, 20 insertions(+)
diff --git a/src/gal
